added yosys-abc and volare,fix syntax error ,end synthesys with genus #828
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Vasco-Luz
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| @@ -25,7 +25,7 @@ set_db stdout_log genus.log | |||
| set_db information_level 7 | |||
| set_db super_thread_debug_directory st_part_log | |||
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| set_db hdl_error_on_latch true | |||
| set_db hdl_error_on_latch false | |||
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You can't disable this for us! We need this!
You need another if statement: check if the submodules/PICORV32 directory exists and disable the check.
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Also, be careful with language used in the commit messages. They will be public!
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You can't disable this for us! We need this!
You need another if statement: check if the submodules/PICORV32 directory exists and disable the check.
That is a very good solution, will be implemented
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Because the setup dir is not an argument passed to the tcl file, he checks all the filenames (without the path) in $VSRC, and if picorv32.v is found, the error on latches is disabled.
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not acceptable; the script knows exactly where picorv32.v
Jut ask the team how to do this
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OK will be fixed
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It checks using relative paths if the submodule PICORV32 exists. If it exists, it will pass a flag so the TCL script will allow latches. An important thing: because the setup directory doesn't exist on the server (after the SSH), I gave it different names. This is because when the Makefile runs in the build directory locally it will check the setup dir because it actually exists, Inside the server the setup dir never exists because only the build dir is copied.
the variable is being exported because i could not pass the variable to the tcl in other ways.
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setupdir does not exist for external users ; just check if ../src/picorv32.v exists
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it checks if ../src/picorv32.v exists
it also checks if syn_build.tcl exists and if iit exists it sources it.
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Suggestion: build.tcl checks if file syn_build.tcl exists in the same directory and sources it if it exists. Inside syn_build the latch errors disabled. |
Vasco-Luz
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| set_db hdl_error_on_latch true | ||
| set_db hdl_error_on_latch true | ||
| if {[file exists "../src/picorv32.v"]} { |
| @@ -0,0 +1 @@ | |||
| set_db hdl_error_on_latch false | |||
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this file should be in iob-soc/hardware/hardware/syn
Not in lib!
Make sure it is copied to build dir during setup.
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If the user doesn't want to disable the check, she does not include this content in her syn_build.tcl or doesn't include the file at all.
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ok implemented. A iob-soc/hardware/syn folder was created. The folder path was already recognized in iob_module dir_list , so it automaticly copies the syn_build.tl to the buildir/hardware/syn, without having to do changes in iob_module.py.
| @@ -24,8 +24,10 @@ set_db init_hdl_search_path $INCLUDE | |||
| set_db stdout_log genus.log | |||
| set_db information_level 7 | |||
| set_db super_thread_debug_directory st_part_log | |||
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| set_db hdl_error_on_latch true | |||
| set_db hdl_error_on_latch true | |||
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is this needed? Isn't true the default?
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The original code already had it set as true. I didn't even think about that. But I will test and see the default value
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Ok, but I still don't know the answer
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i just tested, the standard the latch error is false. i removed the set from the syn_build.tcl and removed from the set from the build tcl, and it gave no synthesis warnings.
| @@ -740,12 +740,6 @@ def _copy_srcs(cls, exclude_file_list=[], highest_superclass=None): | |||
| ), | |||
| ) | |||
| continue | |||
| elif directory == "hardware/common_src": | |||
| shutil.copytree( | |||
| os.path.join(os.getcwd(), directory), | |||
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this lines is something that i added in an old commit but they serve no purpose, because the directory(common_src) is copied ether way in the last else. and worst maybe they are causing problems with other cores.
Added Yosys (with Yosys-ABC), included Volare into Nix (an open PDK package manager), rectified a Verilog syntax error introduced by myself; a wire named "do" was used, which is a reserved name, so changed it to "doo." Also, modified the synthesis process to properly handle SDC files and deactivated latch errors if pico32.v is present in the sources.
Yosys is an open-source framework for Verilog RTL synthesis. It takes Verilog code as input and produces a synthesized netlist as output, which can then be used for further downstream processing, such as placement and routing. Yosys supports a wide range of synthesis optimizations and transformations, allowing users to achieve efficient and optimized hardware designs.
Yosys-ABC is an extension of the Yosys synthesis framework, integrating the ABC (A System for Sequential Synthesis and Verification) tool for logic synthesis. ABC is a highly optimized and widely used academic synthesis tool developed at the University of California, Berkeley.
Volare is a package manager designed specifically for managing Process Design Kits (PDKs) in the context of semiconductor manufacturing and integrated circuit (IC) design. It simplifies the installation and management of PDKs, which contain the necessary technology files, libraries, and models for designing integrated circuits.
The patches are requirements for the specific versions of Yosys-abc and Yosys