Verilator

hardware/simulation/verilator/Makefile

@@ -7,27 +7,63 @@ SIM_SERVER=$(VSIM_SERVER)
 SIM_USER=$(VSIM_USER)
 SIM_PROC=Vsystem
 
+CONSOLE_CMD=../../../software/console/console -L
+ifeq ($(INIT_MEM),0)
+	CONSOLE_CMD+=-f
+endif
 
 include ../simulation.mk
 
 # remove space between -I and directory for verilator
 INCLUDE_VERI=$(subst -I ,-I,$(INCLUDE))
 
-VSRC_VERI=$(subst system_tb.v,,$(VSRC))
+######################################################################
+# Check for sanity to avoid later confusion
+ifneq ($(words $(CURDIR)),1)
+ $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
+endif
 
-#simulator flags
-VLOG = verilator +1800-2005ext+v --error-limit 1000  -cc  $(INCLUDE_VERI) $(DEFINE)
-#VLOG = verilator +1800-2005ext+v --error-limit 1000  -Wall -cc  $(INCLUDE2) $(DEFINE)
+######################################################################
+# Set up variables
 
-# Add system wrapper to the sources list to be verilated
-VSRC+=system_top.v
+# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
+# package install, and verilator is in your path. Otherwise find the
+# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
+ifeq ($(VERILATOR_ROOT),)
+VERILATOR = verilator
+VERILATOR_COVERAGE = verilator_coverage
+else
+export VERILATOR_ROOT
+VERILATOR = $(VERILATOR_ROOT)/bin/verilator
+VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
+endif
 
+# Verilator flags
+VERILATOR_FLAGS += -cc --exe --build# Generate C++ in executable form and compile it after
+#VERILATOR_FLAGS += -MMD # Generate makefile dependencies (not shown as complicates the Makefile)
+#VERILATOR_FLAGS += -Os -x-assign 0 # Optimize
+VERILATOR_FLAGS += -Wall # Warn abount lint issues; may not want this on less solid designs
+VERILATOR_FLAGS += -Wno-lint -Wno-WIDTH -Wno-PINMISSING -Wno-CASEINCOMPLETE # Disable the warnings
+#VERILATOR_FLAGS += --bbox-unsup # Disable the warning that the code has an assignment statement with a delayed time in front of it
+VERILATOR_FLAGS += --trace # Make waveforms
+#VERILATOR_FLAGS += --assert # Check SystemVerilog assertions
+#VERILATOR_FLAGS += --coverage # Generate coverage analysis
+#VERILATOR_FLAGS += --debug # Run Verilator in debug mode
+#VERILATOR_FLAGS += --gdbbt # Add this trace to get a backtrace in gdb
+VERILATOR_FLAGS += +1800-2005ext+v # Use SystemVerilog 2005 with file extension .v
+VERILATOR_FLAGS += --error-limit 1000 # Exit if number of errors passes 1000
+
+# Verilator source files
+VERILATOR_INPUT = $(INCLUDE_VERI) $(DEFINE) $(VSRC) --top-module system_top system_tb.cpp
+######################################################################
 #run the simulator
 run: $(VSRC) $(VHDR) $(IMAGES)
-	$(VLOG) $(VSRC_VERI) --trace --top-module system -Wno-WIDTH -Wno-PINMISSING -Wno-fatal --exe system_tb.cpp
-	make -C obj_dir -j -f Vsystem.mk Vsystem
-	cp obj_dir/Vsystem Vsystem
-	./Vsystem
+	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
+	#$(MAKE) -j -C obj_dir -f Vsystem_top.mk
+	-pkill -f console
+	$(CONSOLE_CMD) &
+	cp obj_dir/Vsystem_top Vsystem_top
+	./Vsystem_top
 
 
 clean: hw-clean

hardware/simulation/verilator/system_tb.cpp

@@ -18,103 +18,143 @@
 // other macros
 #define FREQ 100000000
 #define BAUD 5000000
-#define CLK_PERIOD 10 // 20 ns
+#define CLK_PERIOD 10000 // 20 ns
 
 #define CONSOLE_DIR "../../../software/console/"
 
-unsigned int main_time = 0;
-char = 0;
+vluint64_t main_time = 0;
+VerilatedVcdC* tfp = NULL;
+Vsystem_top* dut = NULL;
 
 double sc_time_stamp () {
   return main_time;
 }
 
-void Timer(Vsystem_top* dut, unsigned int half_cycles){
+void Timer(unsigned int half_cycles){
   for(int i = 0; i<half_cycles; i++){
     dut->clk = !(dut->clk);
     dut->eval();
     tfp->dump(main_time);
-    main_time++;
+    main_time += CLK_PERIOD/2;
   }
 }
 
 // 1-cycle write
-void uartwrite(Vsystem_top* dut, unsigned int cpu_address, char cpu_data){
-    //Timer(1, units="ns")
+void uartwrite(unsigned int cpu_address, char cpu_data){
+
     dut->uart_addr = cpu_address;
     dut->uart_valid = 1;
     dut->uart_wstrb = -1;
     dut->uart_wdata = cpu_data;
-    Timer(dut, 2);
-    //RisingEdge(dut->clk)
-    //Timer(1, units="ns")
+    Timer(2);
     dut->uart_wstrb = 0;
     dut->uart_valid = 0;
 
 }
 
 // 2-cycle read
-void uartread(Vsystem_top* dut, unsigned int cpu_address){
-    //Timer(1, units="ns");
+void uartread(unsigned int cpu_address, char *read_reg){
     dut->uart_addr = cpu_address;
     dut->uart_valid = 1;
-    //RisingEdge(dut->clk);
-    Timer(dut, 2);
-    //Timer(1, units="ns");
-    //print(dut.uart_rdata)
-    read_reg = dut->uart_rdata;
-    Timer(dut, 2);
-    //RisingEdge(dut->clk);
-    //Timer(1, units="ns");
+    Timer(2);
+    *read_reg = dut->uart_rdata;
+    Timer(2);
     dut->uart_valid = 0;
-    return read_reg;
-
 }
 
-void inituart(Vsystem_top* dut){
+void inituart(){
   //pulse reset uart
-  uartwrite(dut, UART_SOFTRESET_ADDR, 1);
-  uartwrite(dut, UART_SOFTRESET_ADDR, 0);
+  uartwrite(UART_SOFTRESET_ADDR, 1);
+  uartwrite(UART_SOFTRESET_ADDR, 0);
   //config uart div factor
-  uartwrite(dut, UART_DIV_ADDR, int(FREQ/BAUD));
+  uartwrite(UART_DIV_ADDR, int(FREQ/BAUD));
   //enable uart for receiving
-  uartwrite(dut, UART_RXEN_ADDR, 1);
-  uartwrite(dut, UART_TXEN_ADDR, 1);
+  uartwrite(UART_RXEN_ADDR, 1);
+  uartwrite(UART_TXEN_ADDR, 1);
 }
 
-int main(int argc, char **argv, char **env)
-{
+int main(int argc, char **argv, char **env){
   Verilated::commandArgs(argc, argv);
   Verilated::traceEverOn(true);
-  Vsystem_top* dut = new Vsystem_top;
-  VerilatedVcdC* tfp = new VerilatedVcdC;
+  dut = new Vsystem_top;
+  tfp = new VerilatedVcdC;
 
-  dut->trace (tfp, 1);
-  tfp->open ("waves.vcd");
+  dut->trace(tfp, 1);
+  tfp->open("waves.vcd");
 
   dut->clk = 0;
   dut->reset = 0;
+  dut->eval();
+  tfp->dump(main_time);
 
   // Reset sequence
   for(int i = 0; i<5; i++){
     dut->clk = !(dut->clk);
     if(i==2 || i==4) dut->reset = !(dut->reset);
     dut->eval();
     tfp->dump(main_time);
-    main_time++;
+    main_time += CLK_PERIOD/2;
+  }
+  dut->uart_valid = 0;
+  dut->uart_wstrb = 0;
+  inituart();
+
+  FILE *soc2cnsl_fd;
+  FILE *cnsl2soc_fd;
+  char cpu_char = 0;
+  char rxread_reg = 0, txread_reg = 0;
+  int n = 0;
+
+  while ((soc2cnsl_fd = fopen("soc2cnsl", "rb+")) == NULL){
+    //printf("Could not open \"soc2cnsl\"\n");
   }
-  dut->uart_valid = 0
-  dut->uart_wstrb = 0
-  inituart(dut);
 
-  printf("\n\nTESTBENCH: connecting");
-  while(1){
-    break;
+  printf("TESTBENCH: connecting\n");
+  while(!Verilated::gotFinish()){
+    if(dut->trap > 0){
+        printf("\nTESTBENCH: force cpu trap exit\n");
+        break;
+    }
+    while(!rxread_reg && !txread_reg){
+      //$write("Loop %d: RX = %x; TX = %x\n", i, rxread_reg[0], txread_reg[0]);
+      uartread(UART_RXREADY_ADDR, &rxread_reg);
+      uartread(UART_TXREADY_ADDR, &txread_reg);
+    }
+    if(rxread_reg){
+      n = fread(&cpu_char, sizeof(char), 1, soc2cnsl_fd);
+      if(n == 0){
+        uartread(UART_RXDATA_ADDR, &cpu_char);
+        //printf("Test 1! %x\n", cpu_char);
+        //$display("%x", cpu_char);
+        fwrite(&cpu_char, sizeof(char), 1, soc2cnsl_fd);
+        rxread_reg = 0;
+      }
+      n = fseek(soc2cnsl_fd, 0, 0);
+    }
+    if(txread_reg){
+      //$write("Enter TX\n");
+      if ((cnsl2soc_fd = fopen("cnsl2soc", "rb")) == NULL){
+        printf("Could not open file cnsl2soc!\n");
+        fclose(soc2cnsl_fd);
+        break;
+      }
+      n = fread(&cpu_char, sizeof(char), 1, cnsl2soc_fd);
+      //printf("Test 2! %x\n", cpu_char);
+      if (n > 0){
+        uartwrite(UART_TXDATA_ADDR, cpu_char);
+        fclose(cnsl2soc_fd);
+        cnsl2soc_fd = fopen("./cnsl2soc", "w");
+      }
+      fclose(cnsl2soc_fd);
+      txread_reg = 0;
+    }
   }
   printf("\nTESTBENCH: finished\n\n");
 
+  dut->final();
   tfp->close();
   delete dut;
+  dut = NULL;
   exit(0);
 
 }