fix regression test

README.md

@@ -28,33 +28,26 @@ so that you do not need to do it every session.
 
 
 ```
-#default sim server
-export SIM_SERVER=pudim-flan.iobundle.com
-export SIM_USER=jsousa
+#ncsim simulator server
+export NCSIM_SERVER=sericaia.iobundle.com
+export NCSIM_USER=jsousa
 
-#default ncsim simulator server
-export NCSIM_SERVER=micro7.lx.it.pt
-export NCSIM_USER=user19
+#quartus server
+export QUAR_SERVER=pudim-flan.iobundle.com
+export QUAR_USER=jsousa
 
-#default fpga build server
-export FPGA_SERVER=pudim-flan.iobundle.com
-export FPGA_USER=jsousa
-
-#default ku40 board server
+#ku40 board server
 export KU40_SERVER=baba-de-camelo.iobundle.com
 export KU40_USER=jsousa
 
-#default cyc5 board server
-export CYC5_SERVER=pudim-flan.iobundle.com
-export CYC5_USER=jsousa
-
-export ASIC_SERVER=micro7.lx.it.pt
-export ASIC_USER=user19
-
+#cadence tools server
+export CADE_SERVER=molotof.iobundle.com
+export CADE_USER=user19
 ```
 
-Make sure the environmental variables for the tools and licenses you use are are
-defined. For example:
+Make sure the environmental variables for the tool paths, licenses servers,
+ports or files are defined in each server in use according to the following
+examples.
 
 ```
 export ALTERAPATH=/path/to/intel/fpga/tools

system.mk

@@ -1,11 +1,11 @@
-#####################################################################
+######################################################################
 #
 # IOb-SoC Configuration File
 #
-#####################################################################
+######################################################################
 
 #
-# PRIMARY PARAMETERS: CAN BE CHANGED BY USERS
+# PRIMARY PARAMETERS: CAN BE CHANGED BY USERS OR OVERRIDEN BY ENV VARS
 #
 
 #FIRMWARE SIZE (LOG2)
@@ -51,16 +51,26 @@ REMOTE_ROOT_DIR ?=sandbox/iob-soc
 #SIMULATION
 #
 
-#default simulator
-SIMULATOR ?=icarus
-
 #produce waveform dump
 VCD ?=0
 
-#set for running remote simulators
-ifeq ($(SIMULATOR),ncsim)
+#set for running (remote) simulators
+#servers and respective users should be environment variables
+#default simulator
+SIMULATOR ?=icarus
+#select according simulators
+ifeq ($(SIMULATOR),icarus)
+	SIM_SERVER=$(IVSIM_SERVER)
+	SIM_USER=$(IVSIM_USER)
+else ifeq ($(SIMULATOR),ncsim)
 	SIM_SERVER=$(NCSIM_SERVER)
 	SIM_USER=$(NCSIM_USER)
+else ifeq ($(SIMULATOR),modelsim)
+	SIM_SERVER=$(MSIM_SERVER)
+	SIM_USER=$(MSIM_USER)
+else ifeq ($(SIMULATOR),verilator)
+	SIM_SERVER=$(VSIM_SERVER)
+	SIM_USER=$(VSIM_USER)
 endif
 
 #
@@ -70,37 +80,51 @@ endif
 #DDR controller address width
 FPGA_DDR_ADDR_W ?=30
 
+
+#set for running (remote) tools and boards
+#servers and respective users should be environment variables
 #default board
 BOARD ?=CYCLONEV-GT-DK
-
-#set for running remote FPGA boards
+#select according to board
 ifeq ($(BOARD),AES-KU040-DB-G)
-	BOARD_SERVER=$(KU40_SERVER)
-	BOARD_USER=$(KU40_USER)
+	FPGA_SERVER=$(VIVA_SERVER)
+	FPGA_USER=$(VIVA_USER)
 	FPGA_OBJ=synth_system.bit
 	FPGA_LOG=vivado.log
-else #default; ifeq ($(BOARD),CYCLONEV-GT-DK)
-	BOARD_SERVER=$(CYC5_SERVER)
-	BOARD_USER=$(CYC5_USER)
+	BOARD_SERVER=$(KU40_SERVER)
+	BOARD_USER=$(KU40_USER)
+else ifeq ($(BOARD),CYCLONEV-GT-DK)
+	FPGA_SERVER=$(QUAR_SERVER)
+	FPGA_USER=$(QUAR_USER)
 	FPGA_OBJ=output_files/top_system.sof
 	FPGA_LOG=output_files/top_system.fit.summary
+	BOARD_SERVER=$(CYC5_SERVER)
+	BOARD_USER=$(CYC5_USER)
 endif
 
 #
 #ASIC COMPILE
 #
-ASIC_NODE=umc130
+#set for running (remote) tools and boards
+#servers and respective users should be environment variables
+#default node
+ASIC_NODE ?=umc130
+#select according to node
+ifeq ($(ASIC_NODE),umc130)
+	ASIC_SERVER=$(CADE_SERVER)
+	ASIC_USER=$(CADE_USER)
+endif
 
 
 #
 # REGRESSION TESTING
 #
 
 #simulators used in regression testing
-SIM_LIST=icarus ncsim
+SIM_LIST ?=icarus ncsim
 
 #boards used for regression testing
-BOARD_LIST=CYCLONEV-GT-DK AES-KU040-DB-G 
+BOARD_LIST ?=CYCLONEV-GT-DK AES-KU040-DB-G