fix pack and unpack, small python formatting issues

IObundle · Jan 15, 2024 · 6002862 · 6002862
1 parent 7438c3f
commit 6002862
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Showing 6 changed files with 59 additions and 8 deletions.
diff --git a/submodules/LIB/hardware/modules/fifo/iob_bfifo/iob_bfifo.py b/submodules/LIB/hardware/modules/fifo/iob_bfifo/iob_bfifo.py
@@ -3,6 +3,7 @@
 from iob_module import iob_module
 from iob_reg_r import iob_reg_r
 
+
 class iob_bfifo(iob_module):
     name = "iob_bfifo"
     version = "V0.10"

diff --git a/submodules/LIB/hardware/modules/iob_pack/hardware/src/iob_pack.v b/submodules/LIB/hardware/modules/iob_pack/hardware/src/iob_pack.v
@@ -46,11 +46,24 @@ module iob_pack #(
    reg read;
    reg write;
 
+   //wrapping control accumulator
+   reg [$clog2(PACKED_DATA_W):0]   wrap_acc_nxt;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_acc;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_incr;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_rem;
+   wire                              wrap_now;
+
    //read unpacked data from external input fifo
    assign read_o = read;
    //write packed data to external output fifo
    assign write_o = write;
 
+    //wrapping control
+   assign wrap_now = wrap_i & (wrap_acc > PACKED_DATA_W_INT);
+   assign wrap_rem = wrap_acc - PACKED_DATA_W_INT;
+   assign wrap_incr = wrap_now? -wrap_acc: wrap_acc+len_i;
+   assign wrap_acc_nxt = wrap_acc + wrap_incr;
+
    //control logic
    always @* begin
       pop = 0;
@@ -74,8 +87,8 @@ module iob_pack #(
             data_read_nxt = 1'b0;
          end
          read = 1'b1;
-      end else if (wrap_i && push_level > 0 && push_level < len_i) begin //wrap up word by pushing zeros
-         push_len = push_level;
+      end else if (wrap_now) begin //wrap up word by pushing zeros
+         push_len = wrap_rem;
          push_data = {UNPACKED_DATA_W{1'b0}};
          push = 1'b1;
       end else if (pop_level >= PACKED_DATA_W_INT && wready_i) begin //pop and write to external output fifo
@@ -118,6 +131,17 @@ module iob_pack #(
       .data_o(data_read)
    );
 
+   //wrapping control accumulator
+   iob_reg_r #(
+      .DATA_W($clog2(PACKED_DATA_W)),
+      .RST_VAL({$clog2(PACKED_DATA_W){1'b0}})
+   ) wrap_acc_reg (
+`include "clk_en_rst_s_s_portmap.vs"
+     .rst_i(rst_i),
+     .data_i(wrap_acc_nxt[$clog2(UNPACKED_DATA_W)-1:0]),
+     .data_o(wrap_acc)
+   );
+
 endmodule
 
 
diff --git a/submodules/LIB/hardware/modules/iob_pack/iob_pack.py b/submodules/LIB/hardware/modules/iob_pack/iob_pack.py
@@ -4,6 +4,7 @@
 from iob_bfifo import iob_bfifo
 from iob_utils import iob_utils
 
+
 class iob_pack(iob_module):
     name = "iob_pack"
     version = "V0.10"

diff --git a/submodules/LIB/hardware/modules/iob_unpack/hardware/src/iob_unpack.v b/submodules/LIB/hardware/modules/iob_unpack/hardware/src/iob_unpack.v
@@ -46,11 +46,24 @@ module iob_unpack #(
    reg                               read;
    reg                               write;
 
+   //wrapping control accumulator
+   reg [$clog2(PACKED_DATA_W):0]   wrap_acc_nxt;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_acc;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_incr;
+   wire [$clog2(PACKED_DATA_W)-1:0]  wrap_rem;
+   wire                              wrap_now;
+
    //read unpacked data from external input fifo
    assign read_o = read;
    //write packed data to external output fifo
    assign write_o = write;
 
+   //wrapping control
+   assign wrap_now = wrap_i & (wrap_acc > PACKED_DATA_W_INT);
+   assign wrap_rem = wrap_acc - PACKED_DATA_W_INT;
+   assign wrap_incr = wrap_now? -wrap_acc: wrap_acc+len_i;
+   assign wrap_acc_nxt = wrap_acc + wrap_incr;
+
    //control logic
    always @* begin
       pop = 0;
@@ -66,13 +79,13 @@ module iob_unpack #(
       data_read_nxt = data_read;
 
       //prioritize pop over push
-      if (pop_level >= len_i && wready_i) begin //pop and write to external output fifo
-         pop = 1'b1;
-         write = 1'b1;
-      end else if (wrap_i && pop_level > 0 && pop_level < len_i) begin //wrap up by popping the remaining data
-         pop_len = pop_level;
+      if (wrap_now) begin //wrap up by popping the remaining data
+         pop_len = wrap_rem;
          pop = 1'b1;
          //no write
+      end else if (pop_level >= len_i && wready_i) begin //pop and write to external output fifo
+         pop = 1'b1;
+         write = 1'b1;
       end else if (data_read && push_level >= PACKED_DATA_W_INT) begin //push and read from external input fifo
          push = 1'b1;         
          if (rready_i) begin
@@ -117,6 +130,17 @@ module iob_unpack #(
      .data_o(data_read)
    );
 
+   //wrapping control accumulator
+   iob_reg_r #(
+      .DATA_W($clog2(PACKED_DATA_W)),
+      .RST_VAL({$clog2(PACKED_DATA_W){1'b0}})
+   ) wrap_acc_reg (
+`include "clk_en_rst_s_s_portmap.vs"
+     .rst_i(rst_i),
+     .data_i(wrap_acc_nxt[$clog2(UNPACKED_DATA_W)-1:0]),
+     .data_o(wrap_acc)
+   );
+
 endmodule
 
 
diff --git a/submodules/LIB/hardware/modules/iob_unpack/iob_unpack.py b/submodules/LIB/hardware/modules/iob_unpack/iob_unpack.py
@@ -4,6 +4,7 @@
 from iob_bfifo import iob_bfifo
 from iob_utils import iob_utils
 
+
 class iob_unpack(iob_module):
     name = "iob_unpack"
     version = "V0.10"

diff --git a/submodules/LIB/scripts/mkregs.py b/submodules/LIB/scripts/mkregs.py
@@ -393,7 +393,7 @@ def write_hwcode(self, table, out_dir, top, csr_if):
 
                     """
                 )
-            
+
         f_inst.write(
             """
             // Core connection wires