Merge pull request #624 from P-Miranda/main-jjts

feat(test): upgrade tests

Makefile

@@ -32,9 +32,9 @@ sim-run:
 	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ sim-run SIMULATOR=$(SIMULATOR)'
 
 sim-test:
-	nix-shell --run 'make clean setup INIT_MEM=1 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-test SIMULATOR=icarus'
-	nix-shell --run 'make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-test SIMULATOR=verilator'
-	nix-shell --run 'make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-test SIMULATOR=verilator'
+	nix-shell --run 'make clean setup INIT_MEM=1 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=icarus'
+	nix-shell --run 'make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator'
+	nix-shell --run 'make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator'
 
 fpga-run:
 	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD)'

submodules/LIB/build.mk

@@ -128,11 +128,8 @@ sim-debug:
 sim-clean:
 	make -C $(SIM_DIR) clean
 
-sim-test: fw-build
-	make -C $(SIM_DIR) test
-
-cov-test: sim-clean
-	make -C $(SIM_DIR) test COV=1
+sim-cov: sim-clean
+	make -C $(SIM_DIR) run COV=1
 
 endif
 
@@ -148,9 +145,6 @@ fpga-build:
 fpga-run:
 	make -C $(FPGA_DIR) run
 
-fpga-test:
-	make -C $(FPGA_DIR) test
-
 fpga-debug:
 	echo "BOARD=$(BOARD)"
 	make -C $(FPGA_DIR) debug
@@ -206,7 +200,7 @@ endif
 #
 test: sim-test fpga-test doc-test
 
-ptest: test syn-test lint-test cov-test
+ptest: test syn-test lint-test sim-cov
 
 dtest: sim-test syn-test fpga-test
 
@@ -226,12 +220,11 @@ clean: fw-clean pc-emul-clean lint-clean sim-clean fpga-clean doc-clean
 	rm -f $(BSP_H)
 
 
-.PHONY: fw-build fpga-fw-build \
-	pc-emul-build pc-emul-run \
+.PHONY: fw-build fpga-fw-build fw-clean \
+	pc-emul-build pc-emul-run pc-emul-clean \
 	lint-test lint-run lint-clean \
-	sim-build sim-run sim-debug \
-	fpga-build fpga-debug \
-	doc-build doc-view doc-debug \
-	test clean debug \
-	sim-test fpga-test doc-test \
-	fw-clean pc-emul-clean sim-clean fpga-clean doc-clean
+	sim-build sim-run sim-debug sim-clean \
+	fpga-build fpga-debug fpga-clean \
+	doc-build doc-view doc-debug doc-test doc-clean \
+	test clean debug
+

submodules/LIB/hardware/fpga/Makefile

@@ -70,7 +70,7 @@ run: build $(RUN_DEPS)
 ifneq ($(NORUN),1)
 ifeq ($(BOARD_SERVER),)
 	cp $(EMB_DIR)/$(NAME)_firmware.bin .
-	$(BOARD_GRAB_CMD) -p '$(FPGA_PROG)' -c '$(CONSOLE_START_CMD)'
+	$(BOARD_GRAB_CMD) -p '$(FPGA_PROG)' -c '$(CONSOLE_START_CMD)'  && test "$$(cat test.log)" = "Test passed!"
 else
 	ssh $(BOARD_USER)@$(BOARD_SERVER) "if [ ! -d $(REMOTE_BUILD_DIR) ]; then mkdir -p $(REMOTE_BUILD_DIR); fi"
 	rsync $(BOARD_SYNC_FLAGS) -avz --delete --force ../.. $(BOARD_USER)@$(BOARD_SERVER):$(REMOTE_BUILD_DIR)
@@ -79,9 +79,6 @@ else
 endif
 endif
 
-test: run
-	sync && sleep 1 && test "$$(cat test.log)" = "Test passed!"
-
 # clean
 clean: $(FPGA_TOOL)-clean
 	find . -maxdepth 1 -type f -not \( -name "Makefile" -o -name "fpga_build.mk" -o -name "uut_build.mk" \) -delete

submodules/LIB/hardware/modules/axis2axi/hardware/simulation/src/axis2axi_tb.v

@@ -101,6 +101,7 @@ module axis2axi_tb;
 
    // Iterators
    integer i;
+   integer fd;
 
    initial begin
 
@@ -161,6 +162,10 @@ module axis2axi_tb;
       $display("Test completed successfully.");
       $display("%c[0m", 27);
 
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
+
       repeat (10) @(posedge clk) #1;
 
       $finish();

submodules/LIB/hardware/modules/div/iob_div_pipe/hardware/simulation/src/iob_div_pipe_tb.v

@@ -28,7 +28,8 @@ module iob_div_pipe_tb;
    reg [DATA_W-1:0]  remainder_out [0:TEST_SZ-1];
 
    integer           i, j;
-
+   integer           fp;
+
    iob_div_pipe # (
                .DATA_W(DATA_W),
                .OPERS_PER_STAGE(OPERS_PER_STAGE)
@@ -68,6 +69,10 @@ module iob_div_pipe_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+
+      fp = $fopen("test.log", "w");
+      $fdisplay(fp, "Test passed!");
+
       #(5 * clk_period) $finish();
    end
 

submodules/LIB/hardware/modules/div/iob_div_pipe/hardware/src/iob_div_pipe.v

@@ -1,7 +1,7 @@
 `timescale 1ns / 1ps
 
 module iob_div_pipe #(
-   parameter DATA_W          = 32,
+   parameter DATA_W = 32,
    parameter OPERS_PER_STAGE = 8
 ) (
    input clk_i,

submodules/LIB/hardware/modules/div/iob_div_subshift/hardware/simulation/src/iob_div_subshift_tb.v

@@ -25,6 +25,7 @@ module iob_div_subshift_tb;
    wire [DATA_W-1:0] remainder_out;
 
    integer           i;
+   integer fp;
 
 
    initial begin
@@ -60,12 +61,17 @@ module iob_div_subshift_tb;
          //verify results
          if(quotient_out != quotient[i] || remainder_out != remainder[i])
            $display ("%d / %d = %d with rem %d but got %d with rem %d", dividend[i], divisor[i], quotient[i], remainder[i], quotient_out, remainder_out);
+         else begin
+            fp = $fopen("test.log", "w");
+            $fdisplay(fp, "Test passed!");
+         end
       end
 
       #clk_period;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+
       #(5 * clk_period) $finish();
 
    end

submodules/LIB/hardware/modules/div/iob_div_subshift_frac/hardware/simulation/src/iob_div_subshift_frac_tb.v

@@ -25,7 +25,8 @@ module iob_div_subshift_frac_tb;
    wire [DATA_W-1:0]        remainder_out;
 
    integer           i;
-
+   integer           fp;
+
    initial begin
 
 `ifdef VCD
@@ -60,7 +61,10 @@ module iob_div_subshift_frac_tb;
          //verify results
          if(quotient_out != quotient[i] || remainder_out != remainder[i])
            $display ("%d / %d = %d with rem %d but got %d with rem %d", dividend[i], divisor[i], quotient[i], remainder[i], quotient_out, remainder_out);
-
+         else begin
+            fp = $fopen("test.log", "w");
+            $fdisplay(fp, "Test passed!");
+         end
 
          #1000;
 

submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/simulation/src/iob_fifo_async_tb.v

@@ -73,6 +73,7 @@ module iob_fifo_async_tb;
    wire [    ADDR_W:0] r_level;
 
    integer i, j;  //iterators
+   integer fd;
 
    reg [TESTSIZE*8-1:0] test_data;
    reg [TESTSIZE*8-1:0] read;
@@ -173,6 +174,9 @@ module iob_fifo_async_tb;
       $display("%c[1;34m", 27);
       $display("INFO: TEST PASSED");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       #100 $finish();
    end
 

submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/simulation/src/iob_fifo_sync_tb.v

@@ -46,6 +46,7 @@ module iob_fifo_sync_tb;
    always #(clk_per / 2) clk = ~clk;
 
    integer i, j;  //iterators
+   integer fd;
 
    reg  [TESTSIZE*MINDATA_W-1:0] test_data;
    reg  [TESTSIZE*MINDATA_W-1:0] read;
@@ -181,6 +182,9 @@ module iob_fifo_sync_tb;
       $display("%c[1;34m", 27);
       $display("INFO: TEST PASSED");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       #(5 * clk_per) $finish();
    end
 

submodules/LIB/hardware/modules/iob_aoi/hardware/simulation/src/iob_aoi_tb.v

@@ -2,30 +2,34 @@
 
 module iob_aoi_tb;
 
-reg	 [3:0] data_i = 0;
-wire data_o;
+   reg	 [3:0] data_i = 0;
+   wire        data_o;
+
+   integer i;
+   integer fp;
 
-integer i;
+   initial begin
+
+      for (i = 0; i < 16; i = i + 1) begin
+      #10 data_i = i;
+         #10 $display("data_i = %b, data_o = %b", data_i, data_o);
+      end
+      #10 $display("%c[1;34m", 27);
+      $display("Test completed successfully.");
+      $display("%c[0m", 27);
+
+      fp = $fopen("test.log", "w");
+      $fdisplay(fp, "Test passed!");
+
+      $finish();
+   end
 
-initial begin
-
-   	for (i = 0; i < 16; i = i + 1) begin
-		#10 data_i = i;
-		#10 $display("data_i = %b, data_o = %b", data_i, data_o);
-	end
-	#10 
-	$display("%c[1;34m", 27);
-	$display("Test completed successfully.");
-	$display("%c[0m", 27);
-	$finish();
-end
-
-iob_aoi iob_aoi_inst (
-	.a_i (data_i[0]),
-	.b_i (data_i[1]),
-	.c_i (data_i[2]),
-	.d_i (data_i[3]),
-	.y_o(data_o)
-);
+   iob_aoi iob_aoi_inst (
+	                 .a_i (data_i[0]),
+	                 .b_i (data_i[1]),
+	                 .c_i (data_i[2]),
+	                 .d_i (data_i[3]),
+	                 .y_o(data_o)
+                         );
 
 endmodule

submodules/LIB/hardware/modules/iob_ctls/hardware/simulation/src/iob_ctls_tb.v

@@ -7,6 +7,7 @@ module iob_ctls_tb;
    wire    [$clog2(W):0] data_o;
 
    integer               i;
+   integer               fd;
 
    initial begin
 `ifdef VCD
@@ -21,6 +22,9 @@ module iob_ctls_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       $finish();
    end
 

submodules/LIB/hardware/modules/iob_prio_enc/hardware/simulation/src/iob_prio_enc_tb.v

@@ -7,6 +7,7 @@ module iob_prio_enc_tb;
    wire    [$clog2(W)-1:0] data_o;
 
    integer                 i;
+   integer                 fd;
 
    initial begin
 `ifdef VCD
@@ -22,6 +23,9 @@ module iob_prio_enc_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       $finish();
    end
 

submodules/LIB/hardware/modules/iob_pulse_gen/hardware/simulation/src/iob_pulse_gen_tb.v

@@ -26,6 +26,7 @@ module iob_pulse_gen_tb;
       );
 
    integer i;
+   integer fd;
    integer duration;
    integer start;
    initial begin
@@ -62,9 +63,18 @@ module iob_pulse_gen_tb;
           $display("%c[1;34m", 27);
           $display("Test completed successfully.");
           $display("%c[0m", 27);
+          fd = $fopen("test.log", "w");
+          $fdisplay(fd, "Test passed!");
+          $fclose(fd);
       end else begin
           $display("Test failed: duration %d\texpected %d", duration, DURATION);
           $display("Test failed: start %d\texpected %d", start, START);
+          fd = $fopen("test.log", "w");
+          $fdisplay(fd, "Test failed: duration %d\texpected %d", duration, DURATION);
+          $fdisplay(fd, "Test failed: start %d\texpected %d", start, START);
+          $fclose(fd);
+
+
       end
       #(10*clk_per) $finish;
    end // initial begin

submodules/LIB/hardware/modules/ram/iob_ram_2p/hardware/simulation/src/iob_ram_2p_tb.v

@@ -19,6 +19,7 @@ module iob_ram_2p_tb;
    wire [`DATA_W-1:0] r_data;
 
    integer i, seq_ini;
+   integer fd;
 
    parameter clk_per = 10;  // clk period = 10 timeticks
 
@@ -86,6 +87,9 @@ module iob_ram_2p_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       $finish();
    end
 

submodules/LIB/hardware/modules/ram/iob_ram_2p_be/hardware/simulation/src/iob_ram_2p_be_tb.v

@@ -20,6 +20,7 @@ module iob_ram_2p_be_tb;
    wire [`DATA_W-1:0] r_data;
 
    integer i, seq_ini;
+   integer fd;
 
    parameter clk_per = 10;  // clk period = 10 timeticks
 
@@ -87,6 +88,9 @@ module iob_ram_2p_be_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       $finish();
    end
 

submodules/LIB/hardware/modules/ram/iob_ram_2p_tiled/hardware/simulation/src/iob_ram_2p_tiled_tb.v

@@ -18,6 +18,7 @@ module iob_ram_2p_tiled_tb;
 
    integer i, seq_ini;
    integer test, base_block;
+   integer fd;
 
    parameter clk_per = 10;  // clk period = 10 timeticks
 
@@ -102,6 +103,9 @@ module iob_ram_2p_tiled_tb;
       $display("%c[1;34m", 27);
       $display("Test completed successfully.");
       $display("%c[0m", 27);
+      fd = $fopen("test.log", "w");
+      $fdisplay(fd, "Test passed!");
+      $fclose(fd);
       $finish();
    end
 endmodule