Merge pull request #314 from PedroAntunes178/verilator

Verilator
IObundle · Feb 15, 2022 · 14796f2 · 14796f2
2 parents 0af3abc + 322cc00
commit 14796f2
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Showing 2 changed files with 18 additions and 16 deletions.
diff --git a/hardware/simulation/icarus/Makefile b/hardware/simulation/icarus/Makefile
@@ -4,6 +4,9 @@ defmacro:=-D
 incdir:=-I
 
 CONSOLE_CMD=../../../software/console/console -L
+ifeq ($(INIT_MEM),0)
+	CONSOLE_CMD+=-f
+endif
 SIMULATOR=icarus
 SIM_SERVER=$(IVSIM_SERVER)
 SIM_USER=$(IVSIM_USER)

diff --git a/hardware/testbench/system_core_tb.v b/hardware/testbench/system_core_tb.v
@@ -19,7 +19,8 @@ module system_tb;
   //received by getchar
   reg [31:0]  rxread_reg;
   reg [31:0]  txread_reg;
-  integer soc2cnsl_fd = 0, cnsl2soc_fd = 0, cpu_char = 0;
+  reg [7:0]  cpu_char;
+  integer soc2cnsl_fd = 0, cnsl2soc_fd = 0;
 
 
   //tester uart
@@ -31,7 +32,7 @@ module system_tb;
   wire                   uart_ready;
 
   //iterator
-  integer                i = 0;
+  integer                i = 0, n = 0;
   integer                error;
 
   //got enquiry (connect request)
@@ -66,6 +67,7 @@ module system_tb;
 
 
     gotENQ = 0;
+    cpu_char = 0;
 
     $write("TESTBENCH: connecting\n");
 
@@ -76,44 +78,41 @@ module system_tb;
         //$write("Loop %d: RX = %x; TX = %x\n", i, rxread_reg[0], txread_reg[0]);
         cpu_uartread(`UART_RXREADY_ADDR, rxread_reg);
         cpu_uartread(`UART_TXREADY_ADDR, txread_reg);
-        i = i+1;
-        if(i>10000) begin
-          #20 $finish;
-        end
       end
       if(rxread_reg) begin
         soc2cnsl_fd = $fopen("soc2cnsl", "wb+");
-        cpu_char = $fgetc(soc2cnsl_fd);
+        n = $fgets(cpu_char, soc2cnsl_fd);
         if (!soc2cnsl_fd)
           $display("Could not open \"soc2cnsl\"");
-        else if((cpu_char < 0)) begin
+        else if(n == 0) begin
           //$write("Enter RX\n");
-          cpu_uartread(`UART_RXREADY_ADDR, cpu_char);
-          $fwrite(soc2cnsl_fd, "%x", cpu_char);
+          cpu_uartread(`UART_RXDATA_ADDR, cpu_char);
+          //$display("%x", cpu_char);
+          $fwriteh(soc2cnsl_fd, "%u", cpu_char);
         end
         $fclose(soc2cnsl_fd);
       end
       if(txread_reg) begin
         //$write("Enter TX\n");
         cnsl2soc_fd = $fopen("cnsl2soc", "rb+");
         if (!cnsl2soc_fd) begin
-          $write("Could not open file cnsl2soc!\n");
+          //$write("Could not open file cnsl2soc!\n");
           $write("TESTBENCH: exiting\n\n");
           $finish;
         end else begin
-          cpu_char = $fgetc(cnsl2soc_fd);
-          while (cpu_char >= 0) begin
-            //$write("Loop TX %x\n", cpu_char);
+          n = $fgets(cpu_char, cnsl2soc_fd);
+          while (n > 0) begin
             cpu_uartwrite(`UART_TXDATA_ADDR, cpu_char);
             txread_reg = 0;
             while(!txread_reg) begin
           	 cpu_uartread(`UART_TXREADY_ADDR, txread_reg);
             end
-            cpu_char = $fgetc(cnsl2soc_fd);
+            n = $fgets(cpu_char, cnsl2soc_fd);
+            n = 0;
           end
           $fclose(cnsl2soc_fd);
           cnsl2soc_fd = $fopen("./cnsl2soc", "w");
-          $fwrite(cnsl2soc_fd, "");
+          $fwriteh(cnsl2soc_fd, "");
           $fclose(cnsl2soc_fd);
         end
       end