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Fix ci.yml; Rename sources; Update submodules. #53

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merged 16 commits into from
Oct 27, 2023
Merged

Fix ci.yml; Rename sources; Update submodules. #53

merged 16 commits into from
Oct 27, 2023

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arturum1
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@arturum1 arturum1 commented Aug 29, 2023 •
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  • Update submodules:
    • Remove LIB
    • Use new IOb-SoC/main
  • Fix ci.yml
  • Add iob_soc_opencryptolinux_ to Verilog sources.
  • Use 3000000 baud rate in simulation when RUN_LINUX=0.

@arturum1 arturum1 marked this pull request as ready for review August 30, 2023 03:12
PedroAntunes178
PedroAntunes178 reviewed Sep 4, 2023
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I agree with the changes. I am just not sure about the UART16550 submodule changes.

@arturum1 arturum1 marked this pull request as draft October 26, 2023 10:22
@arturum1 arturum1 changed the title refactor(wrapper): Rename rst signal to arst in wrappers. Fix ci.yml; Rename sources; Update submodules. Oct 26, 2023
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@arturum1 Is this PR ready for review?
I believe it would be beneficial that it is merged.

@arturum1 arturum1 marked this pull request as ready for review October 27, 2023 14:12
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Sure, I will make PRs for the submodules aswell

This was referenced Oct 27, 2023
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PedroAntunes178 commented Oct 27, 2023 •
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Sure, I will make PRs for the submodules aswell

Only the UART16550 is required.
If possible, mark this PR as ready for review as well: IObundle/iob-uart16550#24.

IOb-PLIC and IOb-CLINT are no longer needed. Therefore, they can be deprecated. Now these peripherals are inside the CPU module.

PS: noticed you already did it. Thank you :)

@PedroAntunes178 PedroAntunes178 merged commit 28e13a4 into IObundle:master Oct 27, 2023
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@arturum1 @PedroAntunes178