SoC: remove PLIC and CLINT submodules, fix axi_ram, passes in Kintex FPGA. #126

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Triggered via pull request October 28, 2023 00:53

PedroAntunes178

opened #58

PedroAntunes178:master

Status Failure

Total duration 38m 18s

Artifacts –

ci.yml

on: pull_request

verilator-baremetal

iverilog-baremetal

cyclonev-baremetal

aes-ku040-baremetal

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2 errors

cyclonev-baremetal

Process completed with exit code 2.

Process completed with exit code 2.