sg13g2_io: verilog: Add more cells

All IO cells, even simple Filler cells, have to be defined for
chip-level simulations. Add more dummy cells for Corner and
Filler cells.

Signed-off-by: Daniel Schultz <[email protected]>

ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v

@@ -243,3 +243,52 @@ endmodule
 module sg13g2_IOPadVdd ();
 endmodule
 `endcelldefine
+
+// type: Corner
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Corner ();
+endmodule
+`endcelldefine
+
+// type: Filler200
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler200 ();
+endmodule
+`endcelldefine
+
+// type: Filler400
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler400 ();
+endmodule
+`endcelldefine
+
+// type: Filler1000
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler1000 ();
+endmodule
+`endcelldefine
+
+// type: Filler2000
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler2000 ();
+endmodule
+`endcelldefine
+
+// type: Filler4000
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler4000 ();
+endmodule
+`endcelldefine
+
+// type: Filler10000
+`timescale 1ns/10ps
+`celldefine
+module sg13g2_Filler10000 ();
+endmodule
+`endcelldefine