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3 wrap existing clashcores uart transmit in packetstream protocol :) #41

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1 change: 1 addition & 0 deletions clash-eth.cabal
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,7 @@ library
Clash.Cores.Ethernet.RGMII
Clash.Cores.Ethernet.PacketStream
Clash.Lattice.ECP5.Prims
Clash.Lattice.ECP5.UART
Clash.Lattice.ECP5.Colorlight.CRG
default-language: Haskell2010
build-depends:
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44 changes: 44 additions & 0 deletions src/Clash/Lattice/ECP5/UART.hs
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
{-# language FlexibleContexts #-}

module Clash.Lattice.ECP5.UART
(uartTxC, uartTxNoBaudGenC) where

import Data.Maybe

import Clash.Cores.Ethernet.PacketStream
import Clash.Cores.UART
import Clash.Prelude
import Protocols
import Protocols.Internal


convertToTx :: Signal dom (Maybe (PacketStreamM2S 1 ())) -> Signal dom (Maybe (BitVector 8))
convertToTx = fmap $ fmap $ (head . _data)

uartTxC
:: forall (dom :: Domain)
(baud :: Nat)
. HiddenClockResetEnable dom
=> ValidBaud dom baud
=> SNat baud
-- ^ The UART baud
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit)
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART
uartTxC baud = fromSignals ckt
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where
ckt (fwd, _) = (PacketStreamS2M <$> ack, CSignal txBit)
where
(txBit, ack) = uartTx baud (convertToTx fwd)

uartTxNoBaudGenC
::
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HiddenClockResetEnable dom
=> BaudGenerator dom
-- ^ The UART baud
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit)
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART
uartTxNoBaudGenC baudGen = fromSignals ckt
where
ckt (fwd, _) = (PacketStreamS2M <$> ack, CSignal txBit)
where
(txBit, ack) = uartTxNoBaudGen baudGen (convertToTx fwd)
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