117 write mac stack tx examples

[t-wallet]

No description provided.

[rowanG077]

The examples don't actually compile cabal test doctests fails. I could fix it with this:

diff --git a/src/Clash/Cores/Ethernet/Examples/TxStack.hs b/src/Clash/Cores/Ethernet/Examples/TxStack.hs
index d2926a0..8fd8e44 100644
--- a/src/Clash/Cores/Ethernet/Examples/TxStack.hs
+++ b/src/Clash/Cores/Ethernet/Examples/TxStack.hs
@@ -10,6 +10,7 @@ Supports any data width bigger than zero.
 
 Example usage:
 
+>>> :set -XFlexibleContexts
 >>> import Clash.Prelude
 >>> import Protocols
 >>> import Protocols.Extra.PacketStream
@@ -21,7 +22,9 @@ for your specific hardware (e.g. RGMII, MII or SGMII) that is adapted to the
 `PacketStream` protocol, i.e. with type:
 
 >>> :{
-dummyTxPhy :: Circuit (PacketStream domEthTx 1 ()) (PacketStream domEthTx 1 ())
+dummyTxPhy
+  :: HiddenClockResetEnable domEthTx
+  => Circuit (PacketStream domEthTx 1 ()) (PacketStream domEthTx 1 ())
 dummyTxPhy = undefined
 :}
 
@@ -32,9 +35,18 @@ ethernet TX domain. All you have to do is specify the data width (in this exampl
 the clock domains, and the TX PHY you want to use.
 
 >>> :{
-myTxStack :: Circuit (PacketStream dom 4 EthernetHeader) (PacketStream domEthTx 1 ())
-myTxStack = txStack @4 |> dummyTxPhy
-}
+myTxStack
+  :: HiddenClockResetEnable dom
+  => KnownDomain domEthTx
+  => HardwareCrc Crc32_ethernet 8 4
+  => Clock domEthTx
+  -> Reset domEthTx
+  -> Enable domEthTx
+  -> Circuit (PacketStream dom 4 EthernetHeader) (PacketStream domEthTx 1 ())
+myTxStack ethTxClk ethTxRst ethTxEn
+  = txStack @4 ethTxClk ethTxRst ethTxEn
+    |> exposeClockResetEnable dummyTxPhy ethTxClk ethTxRst ethTxEn
+:}
 
 Need a TX stack that does it a little different? In this case, you can easily create a
 custom stack by importing the individual components and connecting them via the `|>`
@@ -50,13 +62,16 @@ This custom TX stack processes bytes in the ethernet TX domain. In this case, we
 `asyncFifoC` and `downConverterC`. We also use a bigger interpacket gap than usual, i.e. 16 bytes.
 
 >>> :{
-myCustomTxStack :: Circuit (PacketStream domEthTx 1 EthernetHeader) (PacketStream domEthTx 1 ())
+myCustomTxStack
+  :: HiddenClockResetEnable domEthTx
+  => HardwareCrc Crc32_ethernet 8 1
+  => Circuit (PacketStream domEthTx 1 EthernetHeader) (PacketStream domEthTx 1 ())
 myCustomTxStack =
   macPacketizerC
   |> paddingInserterC d60
   |> fcsInserterC
   |> preambleInserterC
-  |> (exposeClockResetEnable interpacketGapInserterC ethTxClk ethTxRst ethTxEn) d16
+  |> interpacketGapInserterC d16
   |> dummyTxPhy
 :}

The main thing missing is a short explanation about HardwareCrc and link to Clash.Cores.Crc if people want to understand that.

[JLaumen]

I think it might be interesting to add a short note about latency/throughput of the entire stack, since this information is currently missing for most modules in the documentation, but we could also only specify this on a module or component level with #140.

[t-wallet]

I think it might be interesting to add a short note about latency/throughput of the entire stack, since this information is currently missing for most modules in the documentation, but we could also only specify this on a module or component level with #140.

Sure. I think this is easier to add when you have this information about all of the components, so #140 should handle this.