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This repository has been archived by the owner on Sep 6, 2024. It is now read-only.

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Most issues
Fewest issues
Clock domains
Clock domains
We want to be able to use FPGA internal clock with ethernet
Ethernet Data Link Layer
Ethernet Data Link Layer
We want the core to handle the ethernet data link layer
1
Ethernet physical layer
Ethernet physical layer
We want the core to handle the ethernet physical layer
Handle Address Resolution
Handle Address Resolution
We want the core to handle the address resolution protocol
Handle Internet Protocol
Handle Internet Protocol
We want the core to handle the internet protocol
Non-epic-task
Non-epic-task
Any small task not directly falling under an epic
2
Respond to ICMP
Respond to ICMP
We want to respond to ICMP
Route MAC stream
Route MAC stream
We want to be able to route MAC stream to multiple components
UART ethernet
UART ethernet
We want to be able to hook into ethernet packetstream using UART
UDP
UDP
We want to be able transmit and receive user datagram protocol messages
User interface
User interface
We want the core to be easy to use
3