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Merge pull request #16 from GiPHouse/2-setup-ci
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Extend CI
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rowanG077 authored Mar 1, 2024
2 parents 42652cc + 7f8b4af commit cd28ad1
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Showing 5 changed files with 18 additions and 4 deletions.
7 changes: 6 additions & 1 deletion .github/workflows/test.yaml
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Expand Up @@ -3,7 +3,7 @@ on:
push:
pull_request:
jobs:
linting:
file_endings:
runs-on: ubuntu-latest
steps:
- name: git checkout
Expand All @@ -12,6 +12,7 @@ jobs:
run: |
.ci/test_whitespace.sh
build_and_synthesize:
runs-on: ubuntu-latest
steps:
Expand All @@ -25,6 +26,10 @@ jobs:
uses: DeterminateSystems/magic-nix-cache-action@v2
- name: build the nix environment
run: nix-build
- name: check stylish-haskell
run: nix-shell --run "make check_format"
- name: clean linting process
run: nix-shell --run "make clean_tests"
- name: Test suite
run: nix-shell --run "make test"
- name: Test synthesis
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9 changes: 9 additions & 0 deletions Makefile
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Expand Up @@ -6,6 +6,15 @@ clean:

format:
stylish-haskell -c ./.stylish-haskell.yaml -r -i src

check_format:
cp ./.stylish-haskell.yaml ./.stylish-haskell-check.yaml
echo "exit_code: error_on_format" >> ./.stylish-haskell-check.yaml
stylish-haskell -c ./.stylish-haskell-check.yaml -r src

clean_tests:
rm ./.stylish-haskell-check.yaml

test:
cabal test

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2 changes: 1 addition & 1 deletion src/Clash/Cores/Ethernet/RGMII.hs
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Expand Up @@ -118,4 +118,4 @@ rgmiiReceiver channel rxdelay iddr = bundle (ethRxErr, byteStream)
rxData = liftA2 (++#) ethRxData1 ethRxData2

byteStream :: Signal dom (Maybe (BitVector 8))
byteStream = toMaybe <$> ethRxDv <*> rxData
byteStream = toMaybe <$> ethRxDv <*> rxData
2 changes: 1 addition & 1 deletion src/Clash/Lattice/ECP5/Colorlight/TopEntity.hs
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@@ -1,4 +1,4 @@
{-# LANGUAGE NumericUnderscores #-}
{-# language NumericUnderscores #-}

module Clash.Lattice.ECP5.Colorlight.TopEntity ( topEntity ) where

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2 changes: 1 addition & 1 deletion src/Clash/Lattice/ECP5/Prims.hs
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Expand Up @@ -7,7 +7,7 @@
module Clash.Lattice.ECP5.Prims where

import Clash.Annotations.Primitive
import Clash.Explicit.DDR ( ddrOut, ddrIn )
import Clash.Explicit.DDR ( ddrIn, ddrOut )
import Clash.Explicit.Prelude
import Clash.Signal.BiSignal
import Data.String.Interpolate ( i )
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