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Merge pull request #41 from GiPHouse/3-wrap-existing-clashcores-uart-…
…transmit-in-packetstream-protocol 3 wrap existing clashcores uart transmit in packetstream protocol :)
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{-# language FlexibleContexts #-} | ||
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module Clash.Lattice.ECP5.UART | ||
(uartTxC, uartTxNoBaudGenC) where | ||
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import Data.Maybe | ||
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import Clash.Cores.Ethernet.PacketStream | ||
import Clash.Cores.UART | ||
import Clash.Prelude | ||
import Protocols | ||
import Protocols.Internal | ||
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convertToTx :: Signal dom (Maybe (PacketStreamM2S 1 ())) -> Signal dom (Maybe (BitVector 8)) | ||
convertToTx = fmap $ fmap (head . _data) | ||
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uartTxC | ||
:: forall (dom :: Domain) | ||
(baud :: Nat) | ||
. HiddenClockResetEnable dom | ||
=> ValidBaud dom baud | ||
=> SNat baud | ||
-- ^ The UART baud | ||
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit) | ||
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART | ||
uartTxC baud = uartTxNoBaudGenC (baudGenerator baud) | ||
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uartTxNoBaudGenC | ||
:: HiddenClockResetEnable dom | ||
=> BaudGenerator dom | ||
-- ^ The UART baud | ||
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit) | ||
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART | ||
uartTxNoBaudGenC baudGen = fromSignals ckt | ||
where | ||
ckt (fwd, _) = (PacketStreamS2M <$> ack, CSignal txBit) | ||
where | ||
(txBit, ack) = uartTxNoBaudGen baudGen (convertToTx fwd) |