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component now handles backpressure and changed definition to return a…
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… Circuit
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t-wallet committed Mar 8, 2024
1 parent 02d0284 commit 351becc
Showing 1 changed file with 17 additions and 12 deletions.
29 changes: 17 additions & 12 deletions src/Clash/Lattice/ECP5/UART.hs
Original file line number Diff line number Diff line change
@@ -1,26 +1,31 @@
{-#language FlexibleContexts #-}

module Clash.Lattice.ECP5.UART (uartTx') where
module Clash.Lattice.ECP5.UART
(uartTxC) where

import Data.Maybe
import Clash.Cores.Ethernet.PacketStream

import Clash.Prelude
import Protocols
import Clash.Cores.Ethernet.PacketStream
import Clash.Cores.UART
import Protocols
import Protocols.Internal


convert :: Fwd (PacketStream dom 1 ()) -> Signal dom (Maybe (BitVector 8))
convert = fmap $ fmap $ (head . _data)
convertToTx :: Signal dom (Maybe (PacketStreamM2S 1 ())) -> Signal dom (Maybe (BitVector 8))
convertToTx = fmap $ fmap $ (head . _data)

uartTx'
uartTxC
:: forall (dom :: Domain)
(baud :: Nat)
. HiddenClockResetEnable dom
=> ValidBaud dom baud
=> SNat baud
-- ^ The UART baud
-> Signal dom (Maybe (PacketStreamM2S 1 ()))
-- ^ The word to transmit
-> (Signal dom Bit, Signal dom Bool)
-- ^ The output bits for the tx line and an acknowledgement that the word
-- to transmit has been received
uartTx' baud mWord = uartTx baud (convert mWord)
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit)
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART
uartTxC baud = fromSignals ckt
where
ckt (fwd, _) = (PacketStreamS2M <$> ack, CSignal txBit)
where
(txBit, ack) = uartTx baud (convertToTx fwd)

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