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component now handles backpressure and changed definition to return a…
… Circuit
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{-#language FlexibleContexts #-} | ||
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module Clash.Lattice.ECP5.UART (uartTx') where | ||
module Clash.Lattice.ECP5.UART | ||
(uartTxC) where | ||
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import Data.Maybe | ||
import Clash.Cores.Ethernet.PacketStream | ||
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import Clash.Prelude | ||
import Protocols | ||
import Clash.Cores.Ethernet.PacketStream | ||
import Clash.Cores.UART | ||
import Protocols | ||
import Protocols.Internal | ||
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convert :: Fwd (PacketStream dom 1 ()) -> Signal dom (Maybe (BitVector 8)) | ||
convert = fmap $ fmap $ (head . _data) | ||
convertToTx :: Signal dom (Maybe (PacketStreamM2S 1 ())) -> Signal dom (Maybe (BitVector 8)) | ||
convertToTx = fmap $ fmap $ (head . _data) | ||
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uartTx' | ||
uartTxC | ||
:: forall (dom :: Domain) | ||
(baud :: Nat) | ||
. HiddenClockResetEnable dom | ||
=> ValidBaud dom baud | ||
=> SNat baud | ||
-- ^ The UART baud | ||
-> Signal dom (Maybe (PacketStreamM2S 1 ())) | ||
-- ^ The word to transmit | ||
-> (Signal dom Bit, Signal dom Bool) | ||
-- ^ The output bits for the tx line and an acknowledgement that the word | ||
-- to transmit has been received | ||
uartTx' baud mWord = uartTx baud (convert mWord) | ||
-> Circuit (PacketStream dom 1 ()) (CSignal dom Bit) | ||
-- ^ This component receives a PacketStream and converts it to the UART transmitter input while relaying backpressure from the UART | ||
uartTxC baud = fromSignals ckt | ||
where | ||
ckt (fwd, _) = (PacketStreamS2M <$> ack, CSignal txBit) | ||
where | ||
(txBit, ack) = uartTx baud (convertToTx fwd) |