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Bump dependencies, fix new warnings and deprecated/removed functions (#…
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t-wallet authored Aug 14, 2024
1 parent d60e78d commit 01be546
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4 changes: 2 additions & 2 deletions clash-eth.cabal
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ common common-options
Cabal,

-- clash-prelude will set suitable version bounds for the plugins and clash-ghc
clash-prelude >= 1.6.4 && < 1.8,
clash-prelude >= 1.8.1 && < 1.10,
clash-protocols,
ghc-typelits-natnormalise,
ghc-typelits-extra,
Expand Down Expand Up @@ -151,7 +151,7 @@ test-suite doctests
build-depends:
base,
clash-eth,
doctest >= 0.17 && <= 0.19,
doctest,
process,

test-suite test-library
Expand Down
2 changes: 1 addition & 1 deletion nix/nixpkgs.nix
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ let
clash-prelude =
self.callCabal2nix "clash-prelude" (sources.clash-compiler + "/clash-prelude") {};
clash-prelude-hedgehog =
self.callCabal2nix "clash-prelude-hedgehoge" (sources.clash-compiler + "/clash-prelude-hedgehog") {};
self.callCabal2nix "clash-prelude-hedgehog" (sources.clash-compiler + "/clash-prelude-hedgehog") {};
clash-lib =
self.callCabal2nix "clash-lib" (sources.clash-compiler + "/clash-lib") {};
clash-ghc =
Expand Down
60 changes: 30 additions & 30 deletions nix/sources.json
Original file line number Diff line number Diff line change
Expand Up @@ -17,35 +17,35 @@
"homepage": null,
"owner": "cchalmers",
"repo": "circuit-notation",
"rev": "618e37578e699df235f2e7150108b6401731919b",
"sha256": "158dnb3jga4c00ngyc9p57x4qsm7gba519gmfrazan91124v9q2p",
"rev": "19b386c4aa3ff690758ae089c7754303f3500cc9",
"sha256": "0qz2w6akxj51kq50rbl88bnjyxzd2798a9sn9jj1z2kak7a6kqbg",
"type": "tarball",
"url": "https://github.com/cchalmers/circuit-notation/archive/618e37578e699df235f2e7150108b6401731919b.tar.gz",
"url": "https://github.com/cchalmers/circuit-notation/archive/19b386c4aa3ff690758ae089c7754303f3500cc9.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz"
},
"clash-compiler": {
"branch": "1.6",
"branch": "1.8",
"description": "Haskell to VHDL/Verilog/SystemVerilog compiler",
"homepage": "https://clash-lang.org/",
"owner": "clash-lang",
"repo": "clash-compiler",
"rev": "611df52fab184d2f7b7aa768df45e788b13889f2",
"sha256": "1f19w01ljl4psbfv5y5mpij97bnsa7s97ljjcwrsadr3jhlvmc2d",
"rev": "3f5dc67c0e526e43a4dd88eb3902e39ed512c166",
"sha256": "022rwif8xkaabw0j3arhyj0hswmh3vq2nx1bbz8rbkp05jm4psgg",
"type": "tarball",
"url": "https://github.com/clash-lang/clash-compiler/archive/611df52fab184d2f7b7aa768df45e788b13889f2.tar.gz",
"url": "https://github.com/clash-lang/clash-compiler/archive/3f5dc67c0e526e43a4dd88eb3902e39ed512c166.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz",
"version": "1.6.4"
"version": "1.8.1"
},
"clash-protocols": {
"branch": "main",
"description": "a battery-included library for dataflow protocols",
"homepage": null,
"owner": "clash-lang",
"repo": "clash-protocols",
"rev": "f7ea04834d396669fe4ef404b03541601a68b136",
"sha256": "1ngspljca2lq1gg3wg2m3sy54whrpnhp62x2w0sw7i446n9wsf1b",
"rev": "907cfd8d74798859a564f66145baad33d9c79273",
"sha256": "11qa45wsvpb3xdhd5acf821bpr19rrrgxl7q9ghwkl113wpyg7i7",
"type": "tarball",
"url": "https://github.com/clash-lang/clash-protocols/archive/f7ea04834d396669fe4ef404b03541601a68b136.tar.gz",
"url": "https://github.com/clash-lang/clash-protocols/archive/907cfd8d74798859a564f66145baad33d9c79273.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz"
},
"doctest-parallel": {
Expand All @@ -54,12 +54,12 @@
"homepage": null,
"owner": "martijnbastiaan",
"repo": "doctest-parallel",
"rev": "112b85b55c63dae1cc52b5216efe03873f1acc06",
"sha256": "1v18an5np0wflg6phycmmhqmcpmn30p0vxaq2wx8ha5af8ckmymb",
"rev": "d73df0a2fd58b0b6aba438eb40aa56d30724e42a",
"sha256": "1k88bkwz2crvb6dafcf6y5y6wm0m2qvds57f3b0rx4id7la4qv89",
"type": "tarball",
"url": "https://github.com/martijnbastiaan/doctest-parallel/archive/112b85b55c63dae1cc52b5216efe03873f1acc06.tar.gz",
"url": "https://github.com/martijnbastiaan/doctest-parallel/archive/d73df0a2fd58b0b6aba438eb40aa56d30724e42a.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz",
"version": "0.2.6"
"version": "0.3.1"
},
"gitignore": {
"branch": "master",
Expand All @@ -79,35 +79,35 @@
"homepage": "",
"owner": "hedgehogqa",
"repo": "haskell-hedgehog",
"rev": "a5b482493733dbdd50482c6e65f0ee8f2e156293",
"sha256": "1ar2nsbsk7490lpc66zaxsqrh0pkgczh26dkkyby78a2svvmx3gx",
"rev": "52c35cabe24de2a1c03e72dde9d04b64f81d1f44",
"sha256": "1f9znljkmrdd4nlfmjfi8kx0fgcysp328rz27099n7bygchpgjr6",
"type": "tarball",
"url": "https://github.com/hedgehogqa/haskell-hedgehog/archive/a5b482493733dbdd50482c6e65f0ee8f2e156293.tar.gz",
"url": "https://github.com/hedgehogqa/haskell-hedgehog/archive/52c35cabe24de2a1c03e72dde9d04b64f81d1f44.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz",
"version": "1.2"
"version": "1.4"
},
"niv": {
"branch": "master",
"description": "Easy dependency management for Nix projects",
"homepage": "https://github.com/nmattia/niv",
"owner": "nmattia",
"repo": "niv",
"rev": "df49d53b71ad5b6b5847b32e5254924d60703c46",
"sha256": "1j5p8mi1wi3pdcq0lfb881p97i232si07nb605dl92cjwnira88c",
"rev": "723f0eeb969a730db3c30f977c2b66b9dce9fe4a",
"sha256": "0016l7230gd2kdh0g2w573r9a2krqb7x4ifcjhhsn4h1bwap7qr0",
"type": "tarball",
"url": "https://github.com/nmattia/niv/archive/df49d53b71ad5b6b5847b32e5254924d60703c46.tar.gz",
"url": "https://github.com/nmattia/niv/archive/723f0eeb969a730db3c30f977c2b66b9dce9fe4a.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz"
},
"nixpkgs": {
"branch": "nixos-22.11",
"branch": "nixpkgs-unstable",
"description": "Nix Packages collection",
"homepage": "",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "175a638c9ae1ab1760728539b5bcfc77d34f6589",
"sha256": "1c7dmhzpjvj9qhkcwwk77l9gmyhf5yrb3ar493knxvldf7vhqajv",
"rev": "e2dd4e18cc1c7314e24154331bae07df76eb582f",
"sha256": "19zbxf7rb787jvyrfhl4z9sn3aisd6xvx6ikybbi75ym9sy39jds",
"type": "tarball",
"url": "https://github.com/NixOS/nixpkgs/archive/175a638c9ae1ab1760728539b5bcfc77d34f6589.tar.gz",
"url": "https://github.com/NixOS/nixpkgs/archive/e2dd4e18cc1c7314e24154331bae07df76eb582f.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz"
},
"tasty-hedgehog": {
Expand All @@ -116,11 +116,11 @@
"homepage": "",
"owner": "qfpl",
"repo": "tasty-hedgehog",
"rev": "1ade0d8e78c32a724f80d4bc39bdb2a55c5de1c6",
"sha256": "00p60dhj2b8jqnv7hkk6ghshmabkhjalxvncz6dfs0wkr19rqr3l",
"rev": "ed07ecef3f6a01572b577b450ba6d58108173125",
"sha256": "1b8y5ibg1ihgf44nyym4g45lwmabymfcjb2nigv93s2fmng9zp6r",
"type": "tarball",
"url": "https://github.com/qfpl/tasty-hedgehog/archive/1ade0d8e78c32a724f80d4bc39bdb2a55c5de1c6.tar.gz",
"url": "https://github.com/qfpl/tasty-hedgehog/archive/ed07ecef3f6a01572b577b450ba6d58108173125.tar.gz",
"url_template": "https://github.com/<owner>/<repo>/archive/<rev>.tar.gz",
"version": "1.4.0.0"
"version": "1.4.0.2"
}
}
1 change: 1 addition & 0 deletions src/Clash/Cores/Ethernet/IP/EthernetStream.hs
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ data EthernetStreamState
toEthernetStreamC
:: forall (dom :: Domain) (dataWidth :: Nat)
. HiddenClockResetEnable dom
=> KnownNat dataWidth
=> Signal dom MacAddress
-- ^ My Mac address
-> Circuit
Expand Down
1 change: 1 addition & 0 deletions src/Clash/Cores/Ethernet/IP/IPPacketizers.hs
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@ data ChecksumS
setChecksumC
:: forall dom dataWidth
. HiddenClockResetEnable dom
=> KnownNat dataWidth
=> KnownDomain dom
=> Circuit (PacketStream dom dataWidth IPv4Header) (PacketStream dom dataWidth IPv4Header)
setChecksumC = Circuit $ \(fwdInS, bwdInS) ->
Expand Down
2 changes: 1 addition & 1 deletion src/Clash/Cores/Ethernet/IP/IPv4Types.hs
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ instance Bits IPv4Address where
complement = bitCoerceMap @(BitVector 32) complement
shift a n = bitCoerceMap @(BitVector 32) (`shift` n) a
rotate a n = bitCoerceMap @(BitVector 32) (`rotate` n) a
bitSize = bitSize . bitCoerce @IPv4Address @(BitVector 32)
bitSize = finiteBitSize . bitCoerce @IPv4Address @(BitVector 32)
bitSizeMaybe = bitSizeMaybe . bitCoerce @IPv4Address @(BitVector 32)
isSigned = isSigned . bitCoerce @IPv4Address @(BitVector 32)
testBit = testBit . bitCoerce @IPv4Address @(BitVector 32)
Expand Down
8 changes: 4 additions & 4 deletions src/Clash/Lattice/ECP5/Colorlight/CRG.hs
Original file line number Diff line number Diff line change
Expand Up @@ -90,16 +90,16 @@ crg clkin = (clk50, clkEthTx, rst50, rstEthTx)
where
(clk50, locked50) = pll50 clkin
(clkEthTx, lockedEthTx) = pll125 clkin
rst50 = resetSynchronizer clk50 (unsafeFromLowPolarity locked50)
rstEthTx = resetSynchronizer clkEthTx (unsafeFromLowPolarity lockedEthTx)
rst50 = resetSynchronizer clk50 (unsafeFromActiveLow locked50)
rstEthTx = resetSynchronizer clkEthTx (unsafeFromActiveLow lockedEthTx)

-- | Generate a 50Mhz clock from 25Mhz
pll50
:: Clock Dom25
-- ^ Input 25 Mhz clock
-> (Clock Dom50, Signal Dom50 Bool)
-- ^ Output 50Mhz clock and unsynchronized reset signal
pll50 !_ = (clockGen, unsafeToLowPolarity resetGen)
pll50 !_ = (clockGen, unsafeToActiveLow resetGen)
{-# ANN pll50 (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Clash.Lattice.ECP5.Colorlight.CRG.pll50"
Expand Down Expand Up @@ -159,7 +159,7 @@ pll125
-- ^ Input 25 Mhz clock
-> (Clock DomEthTx, Signal DomEthTx Bool)
-- ^ Output 125Mhz clock and unsynchronized reset signal
pll125 !_ = (clockGen, unsafeToLowPolarity resetGen)
pll125 !_ = (clockGen, unsafeToActiveLow resetGen)
{-# ANN pll125 (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Clash.Lattice.ECP5.Colorlight.CRG.pll125"
Expand Down
6 changes: 3 additions & 3 deletions src/Clash/Lattice/ECP5/Prims.hs
Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,7 @@ ofs1p3bx
-- ^ Data input from fabric
-> Signal dom a
-- ^ Output to pin
ofs1p3bx clk rst en inp = fs1p3bx# "O" clk (unsafeToHighPolarity rst) (fromEnable en) inp
ofs1p3bx clk rst en inp = fs1p3bx# "O" clk (unsafeToActiveHigh rst) (fromEnable en) inp

-- | PIC input flip flip with Asynchronous clear
ifs1p3bx
Expand All @@ -138,7 +138,7 @@ ifs1p3bx
-- ^ Data input from pin
-> Signal dom a
-- ^ Output to fabric
ifs1p3bx clk rst en inp = fs1p3bx# "I" clk (unsafeToHighPolarity rst) (fromEnable en) inp
ifs1p3bx clk rst en inp = fs1p3bx# "I" clk (unsafeToActiveHigh rst) (fromEnable en) inp

fs1p3bx#
:: KnownDomain dom -- 0
Expand All @@ -156,7 +156,7 @@ fs1p3bx#
-- ^ Data input from pin or output register block
-> Signal dom a
-- ^ Output
fs1p3bx# !_ clk rst en inp = let rst' = unsafeFromHighPolarity rst
fs1p3bx# !_ clk rst en inp = let rst' = unsafeFromActiveHigh rst
en' = toEnable en
-- Reset value is defined as 1
resetVal = unpack $ complement 0
Expand Down
6 changes: 3 additions & 3 deletions src/Protocols/Extra/PacketStream.hs
Original file line number Diff line number Diff line change
Expand Up @@ -177,12 +177,12 @@ instance

-- | Circuit to convert a CSignal into a PacketStream. This is unsafe, because it drops backpressure.
unsafeToPacketStream :: Circuit (CSignal dom (Maybe (PacketStreamM2S n a))) (PacketStream dom n a)
unsafeToPacketStream = Circuit (\(CSignal fwdInS, _) -> (CSignal $ pure (), fwdInS))
unsafeToPacketStream = Circuit (\(fwdInS, _) -> (pure (), fwdInS))

-- | Converts a PacketStream into a CSignal.
fromPacketStream :: forall dom n meta. HiddenClockResetEnable dom
=> Circuit (PacketStream dom n meta) (CSignal dom (Maybe (PacketStreamM2S n meta)))
fromPacketStream = forceResetSanity |> Circuit (\(inFwd, _) -> (pure (PacketStreamS2M True), CSignal inFwd))
fromPacketStream = forceResetSanity |> Circuit (\(inFwd, _) -> (pure (PacketStreamS2M True), inFwd))

-- | Ensures a circuit does not send out ready on reset
forceResetSanity :: forall dom n meta. HiddenClockResetEnable dom => Circuit (PacketStream dom n meta) (PacketStream dom n meta)
Expand All @@ -191,7 +191,7 @@ forceResetSanity
where
f (True, _, _) = (PacketStreamS2M False, Nothing)
f (False, fwd, bwd) = (bwd, fwd)
rstLow = unsafeToHighPolarity hasReset
rstLow = unsafeToActiveHigh hasReset

-- | Filter a packet stream based on its metadata,
-- with the predicate wrapped in a @Signal@.
Expand Down
13 changes: 6 additions & 7 deletions src/Protocols/Extra/PacketStream/PacketBuffer.hs
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,8 @@ module Protocols.Extra.PacketStream.PacketBuffer

import Clash.Prelude

import Protocols ( Circuit(..), fromSignals, (|>) )
import Protocols
import Protocols.Extra.PacketStream
import Protocols.Internal ( CSignal(..) )

import Data.Maybe
import Data.Maybe.Extra
Expand Down Expand Up @@ -101,16 +100,16 @@ abortOnBackPressure
HiddenClockResetEnable dom
=> KnownNat dataWidth
=> NFDataX metaType
=> ( CSignal dom (Maybe (PacketStreamM2S dataWidth metaType))
=> ( Signal dom (Maybe (PacketStreamM2S dataWidth metaType))
, Signal dom PacketStreamS2M
)
-> ( CSignal dom ()
-> ( Signal dom ()
, Signal dom (Maybe (PacketStreamM2S dataWidth metaType))
)
-- ^ Does not give backpressure, sends an abort forward instead
abortOnBackPressure (CSignal fwdInS, bwdInS) = (CSignal $ pure (), go <$> bundle (fwdInS, bwdInS))
where
go (fwdIn, bwdIn) = fmap (\pkt -> pkt { _abort = _abort pkt || not (_ready bwdIn) }) fwdIn
abortOnBackPressure (fwdInS, bwdInS) = (pure (), go <$> bundle (fwdInS, bwdInS))
where
go (fwdIn, bwdIn) = fmap (\pkt -> pkt{_abort = _abort pkt || not (_ready bwdIn)}) fwdIn

-- | Packet buffer, a circuit which stores words in a buffer until the packet is complete
-- once a packet is complete it will send the entire packet out at once without stalls.
Expand Down
9 changes: 6 additions & 3 deletions src/Protocols/Extra/PacketStream/Packetizers.hs
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
{-# language AllowAmbiguousTypes #-}
{-# language FlexibleContexts #-}
{-# language RecordWildCards #-}
{-# language UndecidableInstances #-}

{-|
Module : Protocols.Extra.PacketStream.Packetizers
Expand Down Expand Up @@ -245,6 +246,7 @@ depacketizerT
. BitSize header ~ headerBytes * 8
=> BitPack header
=> DepacketizerCt headerBytes dataWidth
=> NFDataX metaIn
=> DeForwardBufSize headerBytes dataWidth <= dataWidth
=> headerBytes <= dataWidth * headerBytes `DivRU` dataWidth
=> (header -> metaIn -> metaOut)
Expand Down Expand Up @@ -341,6 +343,7 @@ depacketizerC
(headerBytes :: Nat) .
( HiddenClockResetEnable dom
, NFDataX metaOut
, NFDataX metaIn
, BitPack header
, BitSize header ~ headerBytes * 8
, KnownNat headerBytes
Expand Down Expand Up @@ -408,8 +411,8 @@ packetizeFromDfT toMetaOut toHeader DfIdle (Data dataIn, bwdIn) = (nextStOut, (b
SNatLE -> (DfIdle, Ack (_ready bwdIn), Just l)
where
l = case compareSNat (SNat @(headerBytes `Mod` dataWidth)) d0 of
SNatLE -> natToNum @(dataWidth - 1)
SNatGT -> natToNum @(headerBytes `Mod` dataWidth - 1)
_ -> natToNum @(dataWidth - 1)
SNatGT -> (DfInsert 0 hdrBuf, Ack False, Nothing)

nextStOut = if _ready bwdIn then nextSt else DfIdle
Expand All @@ -422,8 +425,8 @@ packetizeFromDfT toMetaOut _ st@DfInsert{..} (Data dataIn, bwdIn) = (nextStOut,
outPkt = PacketStreamM2S dataOut newLast (toMetaOut dataIn) False

newLast = toMaybe (_dfCounter == maxBound) $ case compareSNat (SNat @(headerBytes `Mod` dataWidth)) d0 of
SNatLE -> natToNum @(dataWidth - 1)
SNatGT -> natToNum @(headerBytes `Mod` dataWidth - 1)
_ -> natToNum @(dataWidth - 1)

bwdOut = Ack (_ready bwdIn && _dfCounter == maxBound)
nextSt = if _dfCounter == maxBound then DfIdle else DfInsert (succ _dfCounter) newHdrBuf
Expand Down Expand Up @@ -525,8 +528,8 @@ depacketizeToDfT toOut st@Parse {..} (Just (PacketStreamM2S {..}), Ack readyIn)

prematureEnd idx
= case compareSNat (SNat @(headerBytes `Mod` dataWidth)) d0 of
SNatLE -> idx < (natToNum @(dataWidth - 1))
SNatGT -> idx < (natToNum @(headerBytes `Mod` dataWidth - 1))
_ -> idx < (natToNum @(dataWidth - 1))

(nextSt, fwdOut)
= case (_dfDeCounter == 0, _last) of
Expand Down
1 change: 1 addition & 0 deletions tests/Test/Cores/Ethernet/IP/EthernetStream.hs
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ testCircuit
:: forall (dom :: Domain) (dataWidth :: Nat)
. HiddenClockResetEnable dom
=> KnownDomain dom
=> KnownNat dataWidth
=> ArpResponse
-> Circuit (PacketStream dom dataWidth IPv4Address) (PacketStream dom dataWidth EthernetHeader)
testCircuit response = circuit $ \packet -> do
Expand Down
2 changes: 1 addition & 1 deletion tests/Test/Cores/Ethernet/IP/InternetChecksum.hs
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ flipBit :: Int -> Int -> [(Bool, Maybe (C.BitVector 16))] -> [(Bool, Maybe (C.Bi
flipBit listIndex bitIndex bitList = replaceAtIndex listIndex newWord bitList
where
replaceAtIndex :: Int -> a -> [a] -> [a]
replaceAtIndex n item ls = a ++ (item:b) where (a, _ : b) = splitAt n ls
replaceAtIndex n item ls = a ++ (item : drop 1 b) where (a, b) = splitAt n ls

newWord = fb <$> (bitList !! listIndex)

Expand Down

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