aim to find a effective Interconnection between computing units of DSP, if possible, make this interconnection reconfigurable.
- Complex programs require more flexible address access, need to expand configuration information format
- Mount Data Memory on the BUS.
- RFU should be refined to RTL at first and integrate it with ARM Cortex A9 processor on the ZYNQ platform.
- Is there any possible to achieve RTL and TLM codesign????