Generate SVE for 80bit load/stores when possible

[pmatos]

Fixes #4126

[pmatos]

Probably not a big win in practice. A single 80-bit store required 2 stores (64 + 16). Now, we require three instructions: mov + whilelt + st1b. You need three 80-bit stores in a block to get to a draw instruction-wise. The next step would be not to assemble the predicate register every time, which I will do next, but we'll still require in practice at least three stores per block for it to "win" instruction-wise.

[pmatos]

Converting to draft, so it's not merged by mistake.

[pmatos]

This is almost ready - the bit missing is really that the predicate register is not yet being cached. I thought RA would take care of this but... apparently there's still some magic missing.

[pmatos]

@Sonicadvance1 pushed changes with the predicate register caching. It's more general than what we need now but if we generate predicate registers from patterns for other purposes we can use the cache as for that as well.

[pmatos]

I will add the generation of SVE instructions to load/store x87 environment.

[Sonicadvance1]

Nice!

[lioncash]

Just one super minor nit, but looks good overall

[pmatos]

I will add the generation of SVE instructions to load/store x87 environment.

Actually this unfortunately is not worth it due to the fact that predicated SVE ldst seem to be more restrictive than 128bit ldst memory addressing. This means that we lose in address computation if we try to use this in fnsave and fnrstor.

I have some work locally to add offsets to Load/Store MemPredicate and then fold Constants into InlineConstants in ConstProp into these and generate these loads/stores from FNSAVE and FNRSTOR but it turns out not to be worth it so I think this work is now complete.

Thanks for the reviews.