OpcodeDispatcher: Constexpr-ify all the tables possible

FEXCore/Source/CMakeLists.txt

@@ -119,7 +119,6 @@ set (SRCS
   Interface/Core/JIT/Arm64/Arm64Relocations.cpp
   Interface/Core/X86Tables/BaseTables.cpp
   Interface/Core/X86Tables/DDDTables.cpp
-  Interface/Core/X86Tables/EVEXTables.cpp
   Interface/Core/X86Tables/H0F38Tables.cpp
   Interface/Core/X86Tables/H0F3ATables.cpp
   Interface/Core/X86Tables/PrimaryGroupTables.cpp

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -690,12 +690,8 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     }
   } else if (Info->Type == FEXCore::X86Tables::TYPE_GROUP_EVEX) {
     FEXCORE_TELEMETRY_SET(EVEXOpTelem, 1);
-
-    /* uint8_t P1 = */ ReadByte();
-    /* uint8_t P2 = */ ReadByte();
-    /* uint8_t P3 = */ ReadByte();
-    uint8_t EVEXOp = ReadByte();
-    return NormalOp(&EVEXTableOps[EVEXOp], EVEXOp);
+    // EVEX unsupported
+    return false;
   }
 
   LOGMAN_MSG_A_FMT("Invalid instruction decoding type");

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -297,8 +297,7 @@ class OpDispatchBuilder final : public IREmitter {
   };
 
   void UnhandledOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
-  void MOVGPROp(OpcodeArgs);
+  void MOVGPROp(OpcodeArgs, uint32_t SrcIndex);
   void MOVGPRNTOp(OpcodeArgs);
   void MOVVectorAlignedOp(OpcodeArgs);
   void MOVVectorUnalignedOp(OpcodeArgs);
@@ -313,20 +312,16 @@ class OpDispatchBuilder final : public IREmitter {
   void IRETOp(OpcodeArgs);
   void CallbackReturnOp(OpcodeArgs);
   void SecondaryALUOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
-  void ADCOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
-  void SBBOp(OpcodeArgs);
+  void ADCOp(OpcodeArgs, uint32_t SrcIndex);
+  void SBBOp(OpcodeArgs, uint32_t SrcIndex);
   void SALCOp(OpcodeArgs);
   void PUSHOp(OpcodeArgs);
   void PUSHREGOp(OpcodeArgs);
   void PUSHAOp(OpcodeArgs);
-  template<uint32_t SegmentReg>
-  void PUSHSegmentOp(OpcodeArgs);
+  void PUSHSegmentOp(OpcodeArgs, uint32_t SegmentReg);
   void POPOp(OpcodeArgs);
   void POPAOp(OpcodeArgs);
-  template<uint32_t SegmentReg>
-  void POPSegmentOp(OpcodeArgs);
+  void POPSegmentOp(OpcodeArgs, uint32_t SegmentReg);
   void LEAVEOp(OpcodeArgs);
   void CALLOp(OpcodeArgs);
   void CALLAbsoluteOp(OpcodeArgs);
@@ -335,41 +330,33 @@ class OpDispatchBuilder final : public IREmitter {
   void LoopOp(OpcodeArgs);
   void JUMPOp(OpcodeArgs);
   void JUMPAbsoluteOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
-  void TESTOp(OpcodeArgs);
+  void TESTOp(OpcodeArgs, uint32_t SrcIndex);
   void MOVSXDOp(OpcodeArgs);
   void MOVSXOp(OpcodeArgs);
   void MOVZXOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
-  void CMPOp(OpcodeArgs);
+  void CMPOp(OpcodeArgs, uint32_t SrcIndex);
   void SETccOp(OpcodeArgs);
   void CQOOp(OpcodeArgs);
   void CDQOp(OpcodeArgs);
   void XCHGOp(OpcodeArgs);
   void SAHFOp(OpcodeArgs);
   void LAHFOp(OpcodeArgs);
-  template<bool ToSeg>
-  void MOVSegOp(OpcodeArgs);
+  void MOVSegOp(OpcodeArgs, bool ToSeg);
   void FLAGControlOp(OpcodeArgs);
   void MOVOffsetOp(OpcodeArgs);
   void CMOVOp(OpcodeArgs);
   void CPUIDOp(OpcodeArgs);
   void XGetBVOp(OpcodeArgs);
   uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit);
   void SHLOp(OpcodeArgs);
-  template<bool SHL1Bit>
-  void SHLImmediateOp(OpcodeArgs);
+  void SHLImmediateOp(OpcodeArgs, bool SHL1Bit);
   void SHROp(OpcodeArgs);
-  template<bool SHR1Bit>
-  void SHRImmediateOp(OpcodeArgs);
+  void SHRImmediateOp(OpcodeArgs, bool SHR1Bit);
   void SHLDOp(OpcodeArgs);
   void SHLDImmediateOp(OpcodeArgs);
   void SHRDOp(OpcodeArgs);
   void SHRDImmediateOp(OpcodeArgs);
-  template<bool IsImmediate, bool Is1Bit>
-  void ASHROp(OpcodeArgs);
-  template<bool Left, bool IsImmediate, bool Is1Bit>
-  void RotateOp(OpcodeArgs);
+  void ASHROp(OpcodeArgs, bool IsImmediate, bool Is1Bit);
   void RotateOp(OpcodeArgs, bool Left, bool IsImmediate, bool Is1Bit);
   void RCROp1Bit(OpcodeArgs);
   void RCROp8x1Bit(OpcodeArgs);
@@ -379,8 +366,6 @@ class OpDispatchBuilder final : public IREmitter {
   void RCLOp(OpcodeArgs);
   void RCLSmallerOp(OpcodeArgs);
 
-  template<uint32_t SrcIndex, enum BTAction Action>
-  void BTOp(OpcodeArgs);
   void BTOp(OpcodeArgs, uint32_t SrcIndex, enum BTAction Action);
 
   void IMUL1SrcOp(OpcodeArgs);
@@ -428,10 +413,8 @@ class OpDispatchBuilder final : public IREmitter {
     FS,
     GS,
   };
-  template<Segment Seg>
-  void ReadSegmentReg(OpcodeArgs);
-  template<Segment Seg>
-  void WriteSegmentReg(OpcodeArgs);
+  void ReadSegmentReg(OpcodeArgs, Segment Seg);
+  void WriteSegmentReg(OpcodeArgs, Segment Seg);
   void EnterOp(OpcodeArgs);
 
   void SGDTOp(OpcodeArgs);
@@ -865,8 +848,7 @@ class OpDispatchBuilder final : public IREmitter {
   void RDTSCPOp(OpcodeArgs);
   void RDPIDOp(OpcodeArgs);
 
-  template<bool ForStore, bool Stream, uint8_t Level>
-  void Prefetch(OpcodeArgs);
+  void Prefetch(OpcodeArgs, bool ForStore, bool Stream, uint8_t Level);
 
   void PSADBW(OpcodeArgs);
 
@@ -2473,10 +2455,6 @@ class OpDispatchBuilder final : public IREmitter {
     }
   }
 
-  Ref Prefetch(bool ForStore, bool Stream, uint8_t CacheLevel, Ref ssa0) {
-    return _Prefetch(ForStore, Stream, CacheLevel, ssa0, Invalid(), MEM_OFFSET_SXTX, 1);
-  }
-
   Ref Pop(uint8_t Size, Ref SP_RMW) {
     Ref Value = _AllocateGPR(false);
     _Pop(Size, SP_RMW, Value);

FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp

@@ -462,17 +462,6 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
   };
 #undef OPD
 
-  auto InstallToTable = [](auto& FinalTable, auto& LocalTable) {
-    for (auto Op : LocalTable) {
-      auto OpNum = std::get<0>(Op);
-      auto Dispatcher = std::get<2>(Op);
-      for (uint8_t i = 0; i < std::get<1>(Op); ++i) {
-        LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].OpcodeDispatcher == nullptr, "Duplicate Entry");
-        FinalTable[OpNum + i].OpcodeDispatcher = Dispatcher;
-      }
-    }
-  };
-
   InstallToTable(FEXCore::X86Tables::VEXTableOps, AVX128Table);
   InstallToTable(FEXCore::X86Tables::VEXTableGroupOps, VEX128TableGroupOps);
   if (CTX->HostFeatures.SupportsPMULL_128Bit) {

FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h

@@ -9,17 +9,17 @@ constexpr inline std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> OpDispat
 
   {0x08, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_OR, FEXCore::IR::IROps::OP_ATOMICFETCHOR, 0>},
 
-  {0x10, 6, &OpDispatchBuilder::ADCOp<0>},
+  {0x10, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 0>},
 
-  {0x18, 6, &OpDispatchBuilder::SBBOp<0>},
+  {0x18, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SBBOp, 0>},
 
   {0x20, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_ANDWITHFLAGS, FEXCore::IR::IROps::OP_ATOMICFETCHAND, 0>},
 
   {0x28, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_SUB, FEXCore::IR::IROps::OP_ATOMICFETCHSUB, 0>},
 
   {0x30, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_XOR, FEXCore::IR::IROps::OP_ATOMICFETCHXOR, 0>},
 
-  {0x38, 6, &OpDispatchBuilder::CMPOp<0>},
+  {0x38, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::CMPOp, 0>},
   {0x50, 8, &OpDispatchBuilder::PUSHREGOp},
   {0x58, 8, &OpDispatchBuilder::POPOp},
   {0x68, 1, &OpDispatchBuilder::PUSHOp},
@@ -29,13 +29,13 @@ constexpr inline std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> OpDispat
   {0x6C, 4, &OpDispatchBuilder::PermissionRestrictedOp},
 
   {0x70, 16, &OpDispatchBuilder::CondJUMPOp},
-  {0x84, 2, &OpDispatchBuilder::TESTOp<0>},
+  {0x84, 2, &OpDispatchBuilder::Bind<&OpDispatchBuilder::TESTOp, 0>},
   {0x86, 2, &OpDispatchBuilder::XCHGOp},
-  {0x88, 4, &OpDispatchBuilder::MOVGPROp<0>},
+  {0x88, 4, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPROp, 0>},
 
-  {0x8C, 1, &OpDispatchBuilder::MOVSegOp<false>},
+  {0x8C, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVSegOp, false>},
   {0x8D, 1, &OpDispatchBuilder::LEAOp},
-  {0x8E, 1, &OpDispatchBuilder::MOVSegOp<true>},
+  {0x8E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVSegOp, true>},
   {0x8F, 1, &OpDispatchBuilder::POPOp},
   {0x90, 8, &OpDispatchBuilder::XCHGOp},
 
@@ -49,11 +49,11 @@ constexpr inline std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> OpDispat
   {0xA4, 2, &OpDispatchBuilder::MOVSOp},
 
   {0xA6, 2, &OpDispatchBuilder::CMPSOp},
-  {0xA8, 2, &OpDispatchBuilder::TESTOp<0>},
+  {0xA8, 2, &OpDispatchBuilder::Bind<&OpDispatchBuilder::TESTOp, 0>},
   {0xAA, 2, &OpDispatchBuilder::STOSOp},
   {0xAC, 2, &OpDispatchBuilder::LODSOp},
   {0xAE, 2, &OpDispatchBuilder::SCASOp},
-  {0xB0, 16, &OpDispatchBuilder::MOVGPROp<0>},
+  {0xB0, 16, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPROp, 0>},
   {0xC2, 2, &OpDispatchBuilder::RETOp},
   {0xC8, 1, &OpDispatchBuilder::EnterOp},
   {0xC9, 1, &OpDispatchBuilder::LEAVEOp},
@@ -82,13 +82,13 @@ constexpr inline std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> OpDispat
 };
 
 constexpr inline std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> OpDispatch_BaseOpTable_32[] = {
-  {0x06, 1, &OpDispatchBuilder::PUSHSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
-  {0x07, 1, &OpDispatchBuilder::POPSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
-  {0x0E, 1, &OpDispatchBuilder::PUSHSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_CS_PREFIX>},
-  {0x16, 1, &OpDispatchBuilder::PUSHSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
-  {0x17, 1, &OpDispatchBuilder::POPSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
-  {0x1E, 1, &OpDispatchBuilder::PUSHSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
-  {0x1F, 1, &OpDispatchBuilder::POPSegmentOp<FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
+  {0x06, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
+  {0x07, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
+  {0x0E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_CS_PREFIX>},
+  {0x16, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
+  {0x17, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
+  {0x1E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
+  {0x1F, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
   {0x27, 1, &OpDispatchBuilder::DAAOp},
   {0x2F, 1, &OpDispatchBuilder::DASOp},
   {0x37, 1, &OpDispatchBuilder::AAAOp},

FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+#include "Interface/Core/OpcodeDispatcher.h"
+
+namespace FEXCore::IR {
+constexpr std::tuple<uint8_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> OpDispatch_DDDTable[] = {
+  {0x0C, 1, &OpDispatchBuilder::PI2FWOp},
+  {0x0D, 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float<4, false>},
+  {0x1C, 1, &OpDispatchBuilder::PF2IWOp},
+  {0x1D, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int<4, false, false>},
+
+  {0x86, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRECP, 4>},
+  {0x87, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRSQRT, 4>},
+
+  {0x8A, 1, &OpDispatchBuilder::PFNACCOp},
+  {0x8E, 1, &OpDispatchBuilder::PFPNACCOp},
+
+  {0x90, 1, &OpDispatchBuilder::VPFCMPOp<1>},
+  {0x94, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMIN, 4>},
+  {0x96, 1, &OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRECP, 4>},
+  {0x97, 1, &OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRSQRT, 4>},
+
+  {0x9A, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFSUB, 4>},
+  {0x9E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADD, 4>},
+
+  {0xA0, 1, &OpDispatchBuilder::VPFCMPOp<2>},
+  {0xA4, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMAX, 4>},
+  // Can be treated as a move
+  {0xA6, 1, &OpDispatchBuilder::MOVVectorUnalignedOp},
+  {0xA7, 1, &OpDispatchBuilder::MOVVectorUnalignedOp},
+
+  {0xAA, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUROp, IR::OP_VFSUB, 4>},
+  {0xAE, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADDP, 4>},
+
+  {0xB0, 1, &OpDispatchBuilder::VPFCMPOp<0>},
+  {0xB4, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMUL, 4>},
+  // Can be treated as a move
+  {0xB6, 1, &OpDispatchBuilder::MOVVectorUnalignedOp},
+  {0xB7, 1, &OpDispatchBuilder::PMULHRWOp},
+
+  {0xBB, 1, &OpDispatchBuilder::PSWAPDOp},
+  {0xBF, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VURAVG, 1>},
+};
+
+} // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+#include "Interface/Core/OpcodeDispatcher.h"
+
+namespace FEXCore::IR {
+#define OPD(prefix, opcode) (((prefix) << 8) | opcode)
+constexpr uint16_t PF_38_NONE = 0;
+constexpr uint16_t PF_38_66 = (1U << 0);
+constexpr uint16_t PF_38_F3 = (1U << 2);
+
+constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> OpDispatch_H0F38Table[] = {
+  {OPD(PF_38_NONE, 0x00), 1, &OpDispatchBuilder::PSHUFBOp},
+  {OPD(PF_38_66, 0x00), 1, &OpDispatchBuilder::PSHUFBOp},
+  {OPD(PF_38_NONE, 0x01), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 2>},
+  {OPD(PF_38_66, 0x01), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 2>},
+  {OPD(PF_38_NONE, 0x02), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 4>},
+  {OPD(PF_38_66, 0x02), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 4>},
+  {OPD(PF_38_NONE, 0x03), 1, &OpDispatchBuilder::PHADDS},
+  {OPD(PF_38_66, 0x03), 1, &OpDispatchBuilder::PHADDS},
+  {OPD(PF_38_NONE, 0x04), 1, &OpDispatchBuilder::PMADDUBSW},
+  {OPD(PF_38_66, 0x04), 1, &OpDispatchBuilder::PMADDUBSW},
+  {OPD(PF_38_NONE, 0x05), 1, &OpDispatchBuilder::PHSUB<2>},
+  {OPD(PF_38_66, 0x05), 1, &OpDispatchBuilder::PHSUB<2>},
+  {OPD(PF_38_NONE, 0x06), 1, &OpDispatchBuilder::PHSUB<4>},
+  {OPD(PF_38_66, 0x06), 1, &OpDispatchBuilder::PHSUB<4>},
+  {OPD(PF_38_NONE, 0x07), 1, &OpDispatchBuilder::PHSUBS},
+  {OPD(PF_38_66, 0x07), 1, &OpDispatchBuilder::PHSUBS},
+  {OPD(PF_38_NONE, 0x08), 1, &OpDispatchBuilder::PSIGN<1>},
+  {OPD(PF_38_66, 0x08), 1, &OpDispatchBuilder::PSIGN<1>},
+  {OPD(PF_38_NONE, 0x09), 1, &OpDispatchBuilder::PSIGN<2>},
+  {OPD(PF_38_66, 0x09), 1, &OpDispatchBuilder::PSIGN<2>},
+  {OPD(PF_38_NONE, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>},
+  {OPD(PF_38_66, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>},
+  {OPD(PF_38_NONE, 0x0B), 1, &OpDispatchBuilder::PMULHRSW},
+  {OPD(PF_38_66, 0x0B), 1, &OpDispatchBuilder::PMULHRSW},
+  {OPD(PF_38_66, 0x10), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 1>},
+  {OPD(PF_38_66, 0x14), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 4>},
+  {OPD(PF_38_66, 0x15), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 8>},
+  {OPD(PF_38_66, 0x17), 1, &OpDispatchBuilder::PTestOp},
+  {OPD(PF_38_NONE, 0x1C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 1>},
+  {OPD(PF_38_66, 0x1C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 1>},
+  {OPD(PF_38_NONE, 0x1D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 2>},
+  {OPD(PF_38_66, 0x1D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 2>},
+  {OPD(PF_38_NONE, 0x1E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 4>},
+  {OPD(PF_38_66, 0x1E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 4>},
+  {OPD(PF_38_66, 0x20), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, true>},
+  {OPD(PF_38_66, 0x21), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, true>},
+  {OPD(PF_38_66, 0x22), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, true>},
+  {OPD(PF_38_66, 0x23), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, true>},
+  {OPD(PF_38_66, 0x24), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, true>},
+  {OPD(PF_38_66, 0x25), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, true>},
+  {OPD(PF_38_66, 0x28), 1, &OpDispatchBuilder::PMULLOp<4, true>},
+  {OPD(PF_38_66, 0x29), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VCMPEQ, 8>},
+  {OPD(PF_38_66, 0x2A), 1, &OpDispatchBuilder::MOVVectorNTOp},
+  {OPD(PF_38_66, 0x2B), 1, &OpDispatchBuilder::PACKUSOp<4>},
+  {OPD(PF_38_66, 0x30), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, false>},
+  {OPD(PF_38_66, 0x31), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, false>},
+  {OPD(PF_38_66, 0x32), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, false>},
+  {OPD(PF_38_66, 0x33), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, false>},
+  {OPD(PF_38_66, 0x34), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, false>},
+  {OPD(PF_38_66, 0x35), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, false>},
+  {OPD(PF_38_66, 0x37), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VCMPGT, 8>},
+  {OPD(PF_38_66, 0x38), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMIN, 1>},
+  {OPD(PF_38_66, 0x39), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMIN, 4>},
+  {OPD(PF_38_66, 0x3A), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMIN, 2>},
+  {OPD(PF_38_66, 0x3B), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMIN, 4>},
+  {OPD(PF_38_66, 0x3C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMAX, 1>},
+  {OPD(PF_38_66, 0x3D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMAX, 4>},
+  {OPD(PF_38_66, 0x3E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMAX, 2>},
+  {OPD(PF_38_66, 0x3F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMAX, 4>},
+  {OPD(PF_38_66, 0x40), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VMUL, 4>},
+  {OPD(PF_38_66, 0x41), 1, &OpDispatchBuilder::PHMINPOSUWOp},
+
+  {OPD(PF_38_NONE, 0xF0), 2, &OpDispatchBuilder::MOVBEOp},
+  {OPD(PF_38_66, 0xF0), 2, &OpDispatchBuilder::MOVBEOp},
+
+  {OPD(PF_38_66, 0xF6), 1, &OpDispatchBuilder::ADXOp},
+  {OPD(PF_38_F3, 0xF6), 1, &OpDispatchBuilder::ADXOp},
+};
+#undef OPD
+
+} // namespace FEXCore::IR