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AVX128: More various instructions #3740

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merged 13 commits into from
Jun 24, 2024
Merged

AVX128: More various instructions #3740

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0c6c4cd
OpcodeDispatcher: make FCMP more compact
alyssarosenzweig Jun 21, 2024
cd03932
OpcodeDispatcher: tweak InsertScalarFCMPOpImpl signature
alyssarosenzweig Jun 21, 2024
2a6d6a9
AVX128: Implement support for v{u,}comis{s,d}
Sonicadvance1 Jun 18, 2024
df232f5
AVX128: Implement support for v{add,sub,mul,fmin,fmax,fdiv,sqrt,rsqrt…
Sonicadvance1 Jun 18, 2024
a0ced2b
AVX128: Implement support for vcmpp{s,d}
Sonicadvance1 Jun 18, 2024
9566dda
AVX128: Implement support for vcmps{s,d}
Sonicadvance1 Jun 18, 2024
3045578
AVX128: Implement vmov{d,q}
Sonicadvance1 Jun 18, 2024
d1dd055
AVX128: Implement support for vpextr{b,w,d,q}
Sonicadvance1 Jun 18, 2024
28d679d
AVX128: Implement support for vpmov{s,z}{b,w,d}{w,d,q}
Sonicadvance1 Jun 18, 2024
b58a57d
AVX128: Implement support for vmovmskp{s,d}
Sonicadvance1 Jun 18, 2024
ad122cf
AVX128: Implement support for vpmovmskb
Sonicadvance1 Jun 18, 2024
abdcaa7
AVX128: Implement support for vpinsr{b,w,d,q}
Sonicadvance1 Jun 18, 2024
9c531d9
AVX128: Implements the various vector shift instructions
Sonicadvance1 Jun 18, 2024
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51 changes: 49 additions & 2 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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Original file line number Diff line number Diff line change
Expand Up @@ -992,6 +992,11 @@ class OpDispatchBuilder final : public IREmitter {
void AVX128_VectorUnaryImpl(OpcodeArgs, IROps IROp, size_t ElementSize);
void AVX128_VectorUnaryImpl(OpcodeArgs, size_t SrcSize, size_t ElementSize, std::function<Ref(size_t ElementSize, Ref Src)> Helper);
void AVX128_VectorBinaryImpl(OpcodeArgs, size_t SrcSize, size_t ElementSize, std::function<Ref(size_t ElementSize, Ref Src1, Ref Src2)> Helper);
void AVX128_VectorShiftWideImpl(OpcodeArgs, size_t ElementSize, IROps IROp);
void AVX128_VectorShiftImmImpl(OpcodeArgs, size_t ElementSize, IROps IROp);

enum class ShiftDirection { RIGHT, LEFT };
void AVX128_ShiftDoubleImm(OpcodeArgs, ShiftDirection Dir);

void AVX128_VMOVAPS(OpcodeArgs);
void AVX128_VMOVSD(OpcodeArgs);
Expand Down Expand Up @@ -1029,6 +1034,49 @@ class OpDispatchBuilder final : public IREmitter {
Ref AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2);
template<size_t ElementSize>
void AVX128_VPSIGN(OpcodeArgs);
template<size_t ElementSize>
void AVX128_UCOMISx(OpcodeArgs);
template<FEXCore::IR::IROps IROp, size_t ElementSize>
void AVX128_VectorScalarInsertALU(OpcodeArgs);
Ref AVX128_VFCMPImpl(size_t ElementSize, Ref Src1, Ref Src2, uint8_t CompType);
template<size_t ElementSize>
void AVX128_VFCMP(OpcodeArgs);
template<size_t ElementSize>
void AVX128_InsertScalarFCMP(OpcodeArgs);
void AVX128_MOVBetweenGPR_FPR(OpcodeArgs);
template<size_t ElementSize>
void AVX128_PExtr(OpcodeArgs);
template<size_t ElementSize, size_t DstElementSize, bool Signed>
void AVX128_ExtendVectorElements(OpcodeArgs);
template<size_t ElementSize>
void AVX128_MOVMSK(OpcodeArgs);
void AVX128_MOVMSKB(OpcodeArgs);
void AVX128_PINSRImpl(OpcodeArgs, size_t ElementSize, const X86Tables::DecodedOperand& Src1Op, const X86Tables::DecodedOperand& Src2Op,
const X86Tables::DecodedOperand& Imm);
void AVX128_VPINSRB(OpcodeArgs);
void AVX128_VPINSRW(OpcodeArgs);
void AVX128_VPINSRDQ(OpcodeArgs);
template<size_t ElementSize>
void AVX128_VPSRA(OpcodeArgs);
template<size_t ElementSize>
void AVX128_VPSLL(OpcodeArgs);
template<size_t ElementSize>
void AVX128_VPSRL(OpcodeArgs);

void AVX128_VariableShiftImpl(OpcodeArgs, IROps IROp);
void AVX128_VPSLLV(OpcodeArgs);
void AVX128_VPSRAVD(OpcodeArgs);
void AVX128_VPSRLV(OpcodeArgs);

template<size_t ElementSize>
void AVX128_VPSRLI(OpcodeArgs);
template<size_t ElementSize>
void AVX128_VPSLLI(OpcodeArgs);
template<size_t ElementSize>
void AVX128_VPSRAI(OpcodeArgs);

void AVX128_VPSRLDQ(OpcodeArgs);
void AVX128_VPSLLDQ(OpcodeArgs);

// End of AVX 128-bit implementation

Expand Down Expand Up @@ -1225,8 +1273,7 @@ class OpDispatchBuilder final : public IREmitter {
Ref InsertScalarRoundImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, const X86Tables::DecodedOperand& Src1Op,
const X86Tables::DecodedOperand& Src2Op, uint64_t Mode, bool ZeroUpperBits);

Ref InsertScalarFCMPOpImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, const X86Tables::DecodedOperand& Src1Op,
const X86Tables::DecodedOperand& Src2Op, uint8_t CompType, bool ZeroUpperBits);
Ref InsertScalarFCMPOpImpl(OpSize Size, uint8_t OpDstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t CompType, bool ZeroUpperBits);

Ref VectorRoundImpl(OpcodeArgs, size_t ElementSize, Ref Src, uint64_t Mode);

Expand Down
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