WIP: Working PR for AVX128

FEXCore/Source/Interface/Config/Config.json.in

@@ -50,8 +50,6 @@
           "DISABLESVE": "disablesve",
           "ENABLEAVX": "enableavx",
           "DISABLEAVX": "disableavx",
-          "ENABLEAVX2": "enableavx2",
-          "DISABLEAVX2": "disableavx2",
           "ENABLEAFP": "enableafp",
           "DISABLEAFP": "disableafp",
           "ENABLELRCPC": "enablelrcpc",
@@ -86,7 +84,6 @@
           "\toff: Default CPU features queried from CPU features",
           "\t{enable,disable}sve: Will force enable or disable sve even if the host doesn't support it",
           "\t{enable,disable}avx: Will force enable or disable avx even if the host doesn't support it",
-          "\t{enable,disable}avx2: Will force enable or disable avx2 even if the host doesn't support it",
           "\t{enable,disable}afp: Will force enable or disable afp even if the host doesn't support it",
           "\t{enable,disable}lrcpc: Will force enable or disable lrcpc even if the host doesn't support it",
           "\t{enable,disable}lrcpc2: Will force enable or disable lrcpc2 even if the host doesn't support it",

FEXCore/Source/Interface/Context/Context.h

@@ -104,6 +104,11 @@ class ContextImpl final : public FEXCore::Context::Context {
   uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, bool WasInJIT, uint64_t* HostGPRs, uint64_t PSTATE) override;
   void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, uint32_t EFLAGS) override;
 
+  Context::XMMRecoveryMode ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low,
+                                                   __uint128_t* YMM_High, Context::XMMRecoveryMode Mode) override;
+  void SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low, const __uint128_t* YMM_High,
+                                Context::XMMRecoveryMode Mode) override;
+
   /**
    * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
    *

FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -19,6 +19,10 @@ namespace CPU {
     {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
     {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT
     {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT_UPPER
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT_UPPER
     {0x0000'0001'0000'0000ULL, 0x0000'0003'0000'0002ULL}, // NAMED_VECTOR_MOVMSKPS_SHIFT
     {0x040B'0E01'0B0E'0104ULL, 0x0C03'0609'0306'090CULL}, // NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE
     {0x0706'0504'FFFF'FFFFULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0110B

FEXCore/Source/Interface/Core/CPUID.cpp

@@ -347,8 +347,7 @@ void CPUIDEmu::SetupHostHybridFlag() {}
 
 
 void CPUIDEmu::SetupFeatures() {
-  // TODO: Enable once AVX is supported.
-  if (false && CTX->HostFeatures.SupportsAVX) {
+  if (CTX->HostFeatures.SupportsAVX) {
     XCR0 |= XCR0_AVX;
   }
 
@@ -417,7 +416,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
             (1 << 9) |                                      // SSSE3
             (0 << 10) |                                     // L1 context ID
             (0 << 11) |                                     // Silicon debug
-            (0 << 12) |                                     // FMA3
+            (SupportsAVX() << 12) |                         // FMA3
             (1 << 13) |                                     // CMPXCHG16B
             (0 << 14) |                                     // xTPR update control
             (0 << 15) |                                     // Perfmon and debug capability
@@ -601,6 +600,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
     // This is due to LRCPC performance on Cortex being abysmal.
     // Only enable EnhancedREPMOVS if SoftwareTSO isn't required OR if MemcpySetTSO is not enabled.
     const uint32_t SupportsEnhancedREPMOVS = CTX->SoftwareTSORequired() == false || MemcpySetTSOEnabled() == false;
+    const uint32_t SupportsVPCLMULQDQ = CTX->HostFeatures.SupportsPMULL_128Bit && SupportsAVX();
 
     // Number of subfunctions
     Res.eax = 0x0;
@@ -609,7 +609,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
               (0 << 2) |                               // SGX
               (SupportsAVX() << 3) |                   // BMI1
               (0 << 4) |                               // Intel Hardware Lock Elison
-              (0 << 5) |                               // AVX2 support
+              (SupportsAVX() << 5) |                   // AVX2 support
               (1 << 6) |                               // FPU data pointer updated only on exception
               (1 << 7) |                               // SMEP support
               (SupportsAVX() << 8) |                   // BMI2
@@ -647,7 +647,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
               (0 << 7) |                                // CET shadow stack
               (0 << 8) |                                // GFNI
               (CTX->HostFeatures.SupportsAES256 << 9) | // VAES
-              (0 << 10) |                               // VPCLMULQDQ
+              (SupportsVPCLMULQDQ << 10) |              // VPCLMULQDQ
               (0 << 11) |                               // AVX512_VNNI
               (0 << 12) |                               // AVX512_BITALG
               (0 << 13) |                               // Intel Total Memory Encryption

FEXCore/Source/Interface/Core/Core.cpp

@@ -216,6 +216,63 @@ uint32_t ContextImpl::ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadSt
   return EFLAGS;
 }
 
+Context::XMMRecoveryMode ContextImpl::ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low,
+                                                              __uint128_t* YMM_High, Context::XMMRecoveryMode Mode) {
+  const bool SupportsAVX = HostFeatures.SupportsAVX;
+  const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
+
+  if (Mode == Context::XMMRecoveryMode::YMM && SupportsAVX) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+
+    if (SupportsConvergedRegisters) {
+      ///< Output wants to de-interleave
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&XMM_Low[i], &Thread->CurrentFrame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
+        memcpy(&YMM_High[i], &Thread->CurrentFrame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
+      }
+    } else {
+      ///< Matches what FEX wants with non-converged registers
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&XMM_Low[i], &Thread->CurrentFrame->State.xmm.sse.data[i][0], sizeof(__uint128_t));
+        memcpy(&YMM_High[i], &Thread->CurrentFrame->State.avx_high[i][0], sizeof(__uint128_t));
+      }
+    }
+
+    return Mode;
+  }
+
+  // Only support SSE, no AVX here, even if requested.
+  memcpy(XMM_Low, Thread->CurrentFrame->State.xmm.sse.data, MaximumRegisters * sizeof(__uint128_t));
+  return Context::XMMRecoveryMode::XMM;
+}
+
+void ContextImpl::SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low,
+                                           const __uint128_t* YMM_High, Context::XMMRecoveryMode Mode) {
+  const bool SupportsAVX = HostFeatures.SupportsAVX;
+  const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
+  if (Mode == Context::XMMRecoveryMode::YMM && SupportsAVX) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+
+    if (SupportsConvergedRegisters) {
+      ///< Output wants to de-interleave
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &XMM_Low[i], sizeof(__uint128_t));
+        memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][2], &YMM_High[i], sizeof(__uint128_t));
+      }
+    } else {
+      ///< Matches what FEX wants with non-converged registers
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &XMM_Low[i], sizeof(__uint128_t));
+        memcpy(&Thread->CurrentFrame->State.avx_high[i][0], &YMM_High[i], sizeof(__uint128_t));
+      }
+    }
+    return;
+  }
+
+  // Only support SSE, no AVX here, even if requested.
+  memcpy(Thread->CurrentFrame->State.xmm.sse.data, XMM_Low, MaximumRegisters * sizeof(__uint128_t));
+}
+
 void ContextImpl::SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, uint32_t EFLAGS) {
   const auto Frame = Thread->CurrentFrame;
   for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_EFLAG_BITS; ++i) {

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -659,6 +659,9 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
       if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) {
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
       }
+      if (options.w) {
+        DecodeInst->Flags |= DecodeFlags::FLAG_OPTION_AVX_W;
+      }
       if (!(map_select >= 1 && map_select <= 3)) {
         LogMan::Msg::EFmt("We don't understand a map_select of: {}", map_select);
         return false;

FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -82,7 +82,6 @@ static void OverrideFeatures(HostFeatures* Features) {
   LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
 
   ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
-  ENABLE_DISABLE_OPTION(SupportsAVX2, AVX2, AVX2);
   ENABLE_DISABLE_OPTION(SupportsSVE128, SVE, SVE);
   ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
   ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
@@ -119,9 +118,6 @@ static void OverrideFeatures(HostFeatures* Features) {
 
   ///< Only force enable SVE256 if SVE is already enabled and ForceSVEWidth is set to >= 256.
   Features->SupportsSVE256 = ForceSVEWidth() && ForceSVEWidth() >= 256;
-  if (!Features->SupportsSVE256) {
-    Features->SupportsAVX = false;
-  }
 }
 
 HostFeatures::HostFeatures() {
@@ -169,8 +165,6 @@ HostFeatures::HostFeatures() {
 
   SupportsAES256 = SupportsAVX && SupportsAES;
 
-  // TODO: AVX2 is currently unsupported. Disable until the remaining features are implemented.
-  SupportsAVX2 = false;
   SupportsBMI1 = true;
   SupportsBMI2 = true;
   SupportsCLWB = true;
@@ -257,7 +251,6 @@ HostFeatures::HostFeatures() {
   Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
   SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
   SupportsAVX = true;
-  SupportsAVX2 = true;
   SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
   SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
   SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
@@ -282,5 +275,10 @@ HostFeatures::HostFeatures() {
 #endif
   SupportsPreserveAllABI = FEXCORE_HAS_PRESERVE_ALL_ATTR;
   OverrideFeatures(this);
+  FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
+  if (!Is64BitMode()) {
+    ///< Always disable AVX in 32-bit mode.
+    SupportsAVX = false;
+  }
 }
 } // namespace FEXCore

FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -355,6 +355,31 @@ DEF_OP(Vector_FToF) {
   }
 }
 
+DEF_OP(Vector_FToF2) {
+  const auto Op = IROp->C<IR::IROp_Vector_FToF2>();
+
+  const auto ElementSize = Op->Header.ElementSize;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
+  const auto Conv = (ElementSize << 8) | Op->SrcElementSize;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
+
+  switch (Conv) {
+  case 0x0402:   // Float <- Half
+  case 0x0804: { // Double <- Float
+    fcvtl2(SubEmitSize, Dst.D(), Vector.D());
+    break;
+  }
+  case 0x0204:   // Half <- Float
+  case 0x0408: { // Float <- Double
+    fcvtn2(SubEmitSize, Dst.D(), Vector.D());
+    break;
+  }
+  default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF2 Type : 0x{:04x}", Conv); break;
+  }
+}
+
 DEF_OP(Vector_FToI) {
   const auto Op = IROp->C<IR::IROp_Vector_FToI>();
   const auto OpSize = IROp->Size;