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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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alyssarosenzweig committed Apr 30, 2024
1 parent fb2cbdf commit e60416d
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Showing 66 changed files with 51,525 additions and 37,961 deletions.
80 changes: 60 additions & 20 deletions unittests/InstructionCountCI/AFP/H0F3A.json
Original file line number Diff line number Diff line change
Expand Up @@ -11,103 +11,143 @@
},
"Instructions": {
"roundss xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintn s16, s17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintn s4, s3",
"mov v16.16b, v4.16b"
]
},
"roundss xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintm s16, s17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintm s4, s3",
"mov v16.16b, v4.16b"
]
},
"roundss xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintp s16, s17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintp s4, s3",
"mov v16.16b, v4.16b"
]
},
"roundss xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintz s16, s17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintz s4, s3",
"mov v16.16b, v4.16b"
]
},
"roundss xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frinti s16, s17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frinti s4, s3",
"mov v16.16b, v4.16b"
]
},
"roundsd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintn d16, d17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintn d4, d3",
"mov v16.16b, v4.16b"
]
},
"roundsd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintm d16, d17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintm d4, d3",
"mov v16.16b, v4.16b"
]
},
"roundsd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintp d16, d17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintp d4, d3",
"mov v16.16b, v4.16b"
]
},
"roundsd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintz d16, d17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frintz d4, d3",
"mov v16.16b, v4.16b"
]
},
"roundsd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 5,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frinti d16, d17"
"mov v2.16b, v16.16b",
"mov v3.16b, v17.16b",
"mov v4.16b, v2.16b",
"frinti d4, d3",
"mov v16.16b, v4.16b"
]
}
}
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19 changes: 13 additions & 6 deletions unittests/InstructionCountCI/AFP/SVE256/Secondary.json
Original file line number Diff line number Diff line change
Expand Up @@ -10,23 +10,30 @@
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 6,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"scvtf v16.2s, v2.2s"
"mov z2.d, p7/m, z16.d",
"mov x20, x4",
"ldr d3, [x20]",
"mov z4.d, z2.d",
"scvtf v4.2s, v3.2s",
"mov z16.d, p7/m, z4.d"
]
},
"cvtpi2ps xmm0, mm0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 5,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"scvtf v16.2s, v2.2s"
"mov z2.d, p7/m, z16.d",
"ldr d3, [x28, #768]",
"mov z4.d, z2.d",
"scvtf v4.2s, v3.2s",
"mov z16.d, p7/m, z4.d"
]
}
}
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