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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Oct 22, 2024
1 parent 58a3d17 commit d2a42c0
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Showing 4 changed files with 118 additions and 191 deletions.
7 changes: 2 additions & 5 deletions unittests/InstructionCountCI/FlagM/HotBlocks.json
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Original file line number Diff line number Diff line change
Expand Up @@ -694,7 +694,7 @@
]
},
"pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
"ExpectedInstructionCount": 41,
"ExpectedInstructionCount": 38,
"Comment": [
"A Hat In Time spends at least 5% CPU time in this instruction",
"Comes from vcruntime140.dll wcsstr"
Expand Down Expand Up @@ -731,11 +731,8 @@
"mov w27, #0x0",
"uxth w21, w20",
"mov w22, #0x8",
"lsr w0, w21, #0",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"rbit w0, w21",
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
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166 changes: 66 additions & 100 deletions unittests/InstructionCountCI/FlagM/Secondary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1031,45 +1031,37 @@
]
},
"cmpxchg cl, bl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"ExpectedArm64ASM": [
"uxtb w20, w6",
"uxtb w21, w7",
"uxtb x22, w4",
"eor w27, w22, w21",
"lsl w0, w22, #24",
"cmp w0, w21, lsl #24",
"sub w26, w22, w21",
"bfxil x4, x21, #0, #8",
"csel x20, x20, x21, eq",
"eor w27, w4, w7",
"lsl w0, w4, #24",
"cmp w0, w7, lsl #24",
"sub w26, w4, w7",
"bfxil x4, x7, #0, #8",
"csel x20, x6, x7, eq",
"bfxil x7, x20, #0, #8"
]
},
"cmpxchg cx, bx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"ExpectedArm64ASM": [
"uxth w20, w6",
"uxth w21, w7",
"uxth x22, w4",
"eor w27, w22, w21",
"lsl w0, w22, #16",
"cmp w0, w21, lsl #16",
"sub w26, w22, w21",
"bfxil x4, x21, #0, #16",
"csel x20, x20, x21, eq",
"eor w27, w4, w7",
"lsl w0, w4, #16",
"cmp w0, w7, lsl #16",
"sub w26, w4, w7",
"bfxil x4, x7, #0, #16",
"csel x20, x6, x7, eq",
"bfxil x7, x20, #0, #16"
]
},
"cmpxchg ecx, ebx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"mov w20, w6",
"mov w21, w7",
"mov w22, w4",
"eor w27, w22, w21",
"subs w26, w22, w21",
"csel x4, x4, x21, eq",
"csel x7, x20, x7, eq"
"mov w20, w7",
"eor w27, w4, w20",
"subs w26, w4, w20",
"csel x4, x4, x20, eq",
"csel x7, x6, x7, eq"
]
},
"cmpxchg rcx, rbx": {
Expand All @@ -1096,17 +1088,14 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w6",
"uxtb w21, w4",
"uxtb x22, w4",
"eor w27, w22, w21",
"lsl w0, w22, #24",
"cmp w0, w21, lsl #24",
"sub w26, w22, w21",
"bfxil x4, x20, #0, #8"
"mov w27, #0x0",
"lsl w0, w4, #24",
"cmp w0, w4, lsl #24",
"sub w26, w4, w4",
"bfxil x4, x6, #0, #8"
]
},
"cmpxchg [rax], bl": {
Expand All @@ -1126,17 +1115,14 @@
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w6",
"uxth w21, w4",
"uxth x22, w4",
"eor w27, w22, w21",
"lsl w0, w22, #16",
"cmp w0, w21, lsl #16",
"sub w26, w22, w21",
"bfxil x4, x20, #0, #16"
"mov w27, #0x0",
"lsl w0, w4, #16",
"cmp w0, w4, lsl #16",
"sub w26, w4, w4",
"bfxil x4, x6, #0, #16"
]
},
"cmpxchg [rax], bx": {
Expand All @@ -1156,30 +1142,27 @@
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w6",
"mov w21, w4",
"mov w22, w4",
"eor w27, w22, w21",
"subs w26, w22, w21",
"mov x4, x20"
"mov w20, w4",
"eor w27, w4, w20",
"subs w26, w4, w20",
"mov x4, x6"
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w6",
"mov w21, w4",
"mov w1, w21",
"casal w1, w20, [x4]",
"mov w20, w1",
"cmp w20, w21",
"csel x4, x4, x20, eq",
"eor w27, w21, w20",
"subs w26, w21, w20"
"subs w26, w21, w20",
"csel x4, x4, x20, eq"
]
},
"cmpxchg rax, rbx": {
Expand Down Expand Up @@ -1451,75 +1434,58 @@
]
},
"bsf ax, bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w6",
"uxth w0, w21",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"clz w22, w0",
"csinv w22, w22, wzr, ne",
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16",
"cfinv"
"rbit w0, w6",
"clz w20, w0",
"tst w6, #0xffff",
"csel x20, x4, x20, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsf eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"mov w20, w6",
"lsr w0, w20, #0",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"clz w21, w0",
"csinv w21, w21, wzr, ne",
"cmp w20, #0x0 (0)",
"csel x4, x4, x21, eq"
"rbit w0, w6",
"clz w20, w0",
"tst w6, w6",
"csel x4, x4, x20, eq"
]
},
"bsf rax, rbx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x0, x6",
"cmp x6, #0x0 (0)",
"clz x20, x0",
"csinv x20, x20, xzr, ne",
"cmp x6, #0x0 (0)",
"tst x6, x6",
"csel x4, x4, x20, eq"
]
},
"bsr ax, bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w6",
"mov x0, #0xf",
"lsl w22, w21, #16",
"orr w22, w22, #0x8000",
"clz w22, w22",
"sub x22, x0, x22",
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16",
"cfinv"
"lsl w20, w6, #16",
"clz w20, w20",
"sub x20, x0, x20",
"tst w6, #0xffff",
"csel x20, x4, x20, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsr eax, ebx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov w20, w6",
"mov x0, #0x1f",
"clz w21, w20",
"sub x21, x0, x21",
"cmp w20, #0x0 (0)",
"csel x4, x4, x21, eq"
"clz w20, w6",
"sub x20, x0, x20",
"tst w6, w6",
"csel x4, x4, x20, eq"
]
},
"bsr rax, rbx": {
Expand All @@ -1529,7 +1495,7 @@
"mov x0, #0x3f",
"clz x20, x6",
"sub x20, x0, x20",
"cmp x6, #0x0 (0)",
"tst x6, x6",
"csel x4, x4, x20, eq"
]
},
Expand Down
14 changes: 4 additions & 10 deletions unittests/InstructionCountCI/SSE42_Strings.json
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@
]
},
"pcmpestri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 40,
"Comment": [
"0x66 0x0f 0x3A 0x61"
],
Expand Down Expand Up @@ -118,11 +118,8 @@
"mov w27, #0x0",
"uxth w21, w20",
"mov w22, #0x10",
"lsr w0, w21, #0",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"rbit w0, w21",
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
Expand Down Expand Up @@ -173,7 +170,7 @@
]
},
"pcmpistri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 41,
"ExpectedInstructionCount": 38,
"Comment": [
"0x66 0x0f 0x3A 0x63"
],
Expand Down Expand Up @@ -209,11 +206,8 @@
"mov w27, #0x0",
"uxth w21, w20",
"mov w22, #0x10",
"lsr w0, w21, #0",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"rbit w0, w21",
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
Expand Down
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