Merge pull request #4050 from alyssarosenzweig/sra/move-size

JIT: always use 64-bit moves for SRA
FEX-Emu · Sep 8, 2024 · cd4c224 · cd4c224
2 parents 07f117b + 67c751d
commit cd4c224
Showing 1 changed file with 3 additions and 15 deletions.
diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
@@ -140,11 +140,7 @@ DEF_OP(LoadRegister) {
     const auto reg = StaticRegisters[Op->Reg];
 
     if (GetReg(Node).Idx() != reg.Idx()) {
-      if (OpSize == 4) {
-        mov(GetReg(Node).W(), reg.W());
-      } else {
-        mov(GetReg(Node).X(), reg.X());
-      }
+      mov(GetReg(Node).X(), reg.X());
     }
   } else if (Op->Class == IR::FPRClass) {
     [[maybe_unused]] const auto regSize = HostSupportsAVX256 ? Core::CPUState::XMM_AVX_REG_SIZE : Core::CPUState::XMM_SSE_REG_SIZE;
@@ -170,23 +166,15 @@ DEF_OP(LoadPF) {
   const auto reg = StaticRegisters[StaticRegisters.size() - 2];
 
   if (GetReg(Node).Idx() != reg.Idx()) {
-    if (IROp->Size == 4) {
-      mov(GetReg(Node).W(), reg.W());
-    } else {
-      mov(GetReg(Node).X(), reg.X());
-    }
+    mov(GetReg(Node).X(), reg.X());
   }
 }
 
 DEF_OP(LoadAF) {
   const auto reg = StaticRegisters[StaticRegisters.size() - 1];
 
   if (GetReg(Node).Idx() != reg.Idx()) {
-    if (IROp->Size == 4) {
-      mov(GetReg(Node).W(), reg.W());
-    } else {
-      mov(GetReg(Node).X(), reg.X());
-    }
+    mov(GetReg(Node).X(), reg.X());
   }
 }