Merge pull request #3491 from alyssarosenzweig/rclse/waw

RCLSE: Optimize store-after-store
FEX-Emu · Mar 14, 2024 · ca6b2e4 · ca6b2e4
2 parents 8a3d08e + ed59f73
commit ca6b2e4
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Showing 14 changed files with 897 additions and 1,052 deletions.
diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp
@@ -201,7 +201,7 @@ DEF_OP(VSha256U0) {
   else {
     mov(VTMP1.Q(), Src1.Q());
     sha256su0(VTMP1, Src2);
-    mov(Dst.Q(), Src1.Q());
+    mov(Dst.Q(), VTMP1.Q());
   }
 }
 

diff --git a/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp b/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp
@@ -547,10 +547,20 @@ bool RCLSE::ClassifyContextLoad(FEXCore::IR::IREmitter *IREmit, ContextInfo *Loc
 
 bool RCLSE::ClassifyContextStore(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, uint8_t Size, FEXCore::IR::OrderedNode *CodeNode, FEXCore::IR::OrderedNode *ValueNode) {
   auto Info = FindMemberInfo(LocalInfo, Offset, Size);
+  ContextMemberInfo PreviousMemberInfoCopy = *Info;
   RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode,
                CodeNode);
-  // TODO: Optimize redundant stores.
-  // ContextMemberInfo PreviousMemberInfoCopy = *Info;
+
+  if (PreviousMemberInfoCopy.AccessRegClass == Info->AccessRegClass &&
+      PreviousMemberInfoCopy.AccessOffset == Info->AccessOffset &&
+      PreviousMemberInfoCopy.AccessSize == Size &&
+      PreviousMemberInfoCopy.Accessed == LastAccessType::WRITE) {
+    // This optimizes redundant stores with no intervening load
+    IREmit->Remove(PreviousMemberInfoCopy.StoreNode);
+    return true;
+  }
+
+  // TODO: Optimize the case of partial stores.
   return false;
 }
 

diff --git a/unittests/ASM/Disabled_Tests_Simulator b/unittests/ASM/Disabled_Tests_Simulator
@@ -83,3 +83,6 @@ Test_VEX/vroundpd.asm
 Test_VEX/vroundps.asm
 Test_VEX/vroundsd.asm
 Test_VEX/vroundss.asm
+
+# Simulator doesn't support cycle counter reading
+Test_TwoByte/0F_31.asm
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
@@ -14,7 +14,7 @@
   ],
   "Instructions": {
     "push ax, bx": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 4,
       "Comment": [
         "Mergable 16-bit pushes. May or may not be an optimization."
       ],
@@ -23,12 +23,14 @@
         "push bx"
       ],
       "ExpectedArm64ASM": [
-        "strh w4, [x8, #-2]!",
+        "mov x20, x8",
+        "strh w4, [x20, #-2]!",
+        "mov x8, x20",
         "strh w7, [x8, #-2]!"
       ]
     },
     "push rax, rbx": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 4,
       "Comment": [
         "Mergable 64-bit pushes"
       ],
@@ -37,12 +39,14 @@
         "push rbx"
       ],
       "ExpectedArm64ASM": [
-        "str x4, [x8, #-8]!",
+        "mov x20, x8",
+        "str x4, [x20, #-8]!",
+        "mov x8, x20",
         "str x7, [x8, #-8]!"
       ]
     },
     "adds xmm0, xmm1, xmm2": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "Redundant scalar adds that can get eliminated without AFP."
       ],
@@ -51,9 +55,11 @@
         "addss xmm0, xmm2"
       ],
       "ExpectedArm64ASM": [
+        "mov v2.16b, v16.16b",
         "fadd s0, s16, s17",
-        "mov v16.s[0], v0.s[0]",
-        "fadd s0, s16, s18",
+        "mov v2.s[0], v0.s[0]",
+        "mov v16.16b, v2.16b",
+        "fadd s0, s2, s18",
         "mov v16.s[0], v0.s[0]"
       ]
     },

diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
@@ -15,7 +15,7 @@
   ],
   "Instructions": {
     "adds xmm0, xmm1, xmm2": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 4,
       "Comment": [
         "Redundant scalar operations should get eliminated with AFP"
       ],
@@ -24,8 +24,10 @@
         "addss xmm0, xmm2"
       ],
       "ExpectedArm64ASM": [
-        "fadd s16, s16, s17",
-        "fadd s16, s16, s18"
+        "mov v2.16b, v16.16b",
+        "fadd s2, s16, s17",
+        "mov v16.16b, v2.16b",
+        "fadd s16, s2, s18"
       ]
     }
   }