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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Apr 6, 2024
1 parent 95589f6 commit b54d493
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Showing 4 changed files with 266 additions and 325 deletions.
189 changes: 86 additions & 103 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1676,15 +1676,15 @@
"uxtb w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x24",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #24",
"mov w23, #0x8",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #7, #nzcV"
"mov w0, #0x8",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV"
]
},
"shr al, cl": {
Expand All @@ -1695,14 +1695,14 @@
"uxtb w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x20",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #7, #nzcV"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV"
]
},
"sar al, cl": {
Expand All @@ -1714,12 +1714,12 @@
"sxtb x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x18",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"rol ax, cl": {
Expand Down Expand Up @@ -1943,53 +1943,46 @@
"uxth w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x24",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #16",
"mov w23, #0x10",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #15, #nzcV"
"mov w0, #0x10",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst w22, w22",
"mov w23, #0x20",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #31, #nzcV"
"lsl w4, w20, w21",
"cbz w21, #+0x1c",
"ands w26, w4, w4",
"neg w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsl x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"lsl x4, x20, x5",
"cbz x5, #+0x1c",
"ands x26, x4, x4",
"neg x0, x5",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"shr ax, cl": {
Expand All @@ -2000,50 +1993,45 @@
"uxth w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x20",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #15, #nzcV"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x20",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #31, #nzcV"
"lsr w4, w20, w21",
"cbz w21, #+0x1c",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shr rax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x20",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"lsr x4, x20, x5",
"cbz x5, #+0x1c",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"sar ax, cl": {
Expand All @@ -2055,44 +2043,39 @@
"sxth x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x18",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"asr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x18",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w20, w20, w21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"asr w4, w20, w21",
"cbz w21, #+0x14",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"sar rax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"asr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x18",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"asr x4, x20, x5",
"cbz x5, #+0x14",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"rmif x0, #63, #nzCv"
]
},
"test bl, 1": {
Expand Down
53 changes: 24 additions & 29 deletions unittests/InstructionCountCI/FlagM/Secondary.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -794,19 +794,19 @@
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x23",
"cbz x22, #+0x24",
"cbz w22, #+0x24",
"cmn wzr, w20, lsl #16",
"mov w23, #0x10",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV"
"mov w0, #0x10",
"sub w0, w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 19,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
Expand All @@ -821,19 +821,17 @@
"csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23",
"cbz x22, #+0x24",
"tst w20, w20",
"mov w23, #0x20",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #31, #nzcV"
"cbz w22, #+0x1c",
"ands w26, w20, w20",
"neg w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
Expand All @@ -844,18 +842,15 @@
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x22, x20, x22, eq",
"mov x4, x22",
"csel x4, x20, x22, eq",
"msr nzcv, x23",
"cbz x21, #+0x24",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"cbz x21, #+0x1c",
"ands x26, x4, x4",
"neg x0, x21",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"bts ax, bx": {
Expand Down
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