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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Sep 6, 2024
1 parent 775ec8d commit 1c2ecf0
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Showing 12 changed files with 367 additions and 377 deletions.
16 changes: 8 additions & 8 deletions unittests/InstructionCountCI/AVX128/VEX_map1.json
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Original file line number Diff line number Diff line change
Expand Up @@ -2891,8 +2891,8 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x20, eq",
"ccmn x26, x20, #nzCv, le"
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vucomisd xmm0, xmm1": {
Expand All @@ -2904,8 +2904,8 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x20, eq",
"ccmn x26, x20, #nzCv, le"
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vcomiss xmm0, xmm1": {
Expand All @@ -2917,8 +2917,8 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x20, eq",
"ccmn x26, x20, #nzCv, le"
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vcomisd xmm0, xmm1": {
Expand All @@ -2930,8 +2930,8 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x20, eq",
"ccmn x26, x20, #nzCv, le"
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vaddps xmm0, xmm1, xmm2": {
Expand Down
44 changes: 17 additions & 27 deletions unittests/InstructionCountCI/FlagM/FlagOpts.json
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Original file line number Diff line number Diff line change
Expand Up @@ -203,27 +203,21 @@
},
"Variable rotate-through-carry dead": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 11,
"x86Insts": [
"rcr rax, cl",
"test rax, rdx"
],
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"cbz x20, #+0x20",
"lsr x20, x4, x7",
"cset w21, lo",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x7, #0x1 (1)",
"lsr x23, x4, x23",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"lsl x21, x21, x22",
"orr x4, x20, x21",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV",
"ands x26, x4, x5",
"cfinv"
]
Expand Down Expand Up @@ -290,10 +284,10 @@
"ExpectedArm64ASM": [
"and w26, w4, w6",
"mov x4, x26",
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"and w20, w20, #0x1",
"bfxil x7, x20, #0, #8",
"cmn wzr, w7, lsl #24",
"cfinv",
Expand All @@ -302,7 +296,7 @@
},
"UCOMISS use only PF": {
"x86InstructionCount": 3,
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"x86Insts": [
"ucomiss xmm0, xmm1",
"setnp cl",
Expand All @@ -311,11 +305,7 @@
"ExpectedArm64ASM": [
"fcmp s16, s17",
"cset w26, vc",
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eor w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"bfxil x7, x20, #0, #8",
"bfxil x7, x26, #0, #8",
"subs x26, x4, #0x0 (0)"
]
},
Expand All @@ -328,7 +318,7 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"cmn wzr, w4, lsl #16",
"tst w4, #0xffff",
"cset x20, eq",
"bfxil x4, x20, #0, #8",
"cmn wzr, w7, lsl #24",
Expand All @@ -345,10 +335,10 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"and w20, w4, w6",
"cmn wzr, w20, lsl #16",
"cset x21, eq",
"bfxil x4, x21, #0, #8",
"and w0, w4, w6",
"tst w0, #0xffff",
"cset x20, eq",
"bfxil x4, x20, #0, #8",
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
Expand All @@ -364,10 +354,10 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x89",
"and w20, w4, w20",
"cmn wzr, w20, lsl #24",
"cset x21, ne",
"bfxil x4, x21, #0, #8",
"and w0, w4, w20",
"tst w0, #0xff",
"cset x20, ne",
"bfxil x4, x20, #0, #8",
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
Expand Down
18 changes: 9 additions & 9 deletions unittests/InstructionCountCI/FlagM/Primary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1728,9 +1728,9 @@
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
"eor w21, w21, w21, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w21, w0, w0, lsr #1",
"orr x21, x21, #0xfffffffffffffffe",
"orn x20, x20, x21, ror #62",
"mrs x21, nzcv",
Expand Down Expand Up @@ -1773,9 +1773,9 @@
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
"eor w21, w21, w21, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w21, w0, w0, lsr #1",
"orr x21, x21, #0xfffffffffffffffe",
"orn x20, x20, x21, ror #62",
"mrs x21, nzcv",
Expand Down Expand Up @@ -1847,9 +1847,9 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
"eor w21, w21, w21, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w21, w0, w0, lsr #1",
"orr x21, x21, #0xfffffffffffffffe",
"orn x20, x20, x21, ror #62",
"mrs x21, nzcv",
Expand Down
52 changes: 26 additions & 26 deletions unittests/InstructionCountCI/FlagM/Secondary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -257,9 +257,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w20, w6, w4, ne",
Expand All @@ -271,9 +271,9 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w4, w6, w4, ne",
Expand All @@ -284,9 +284,9 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel x4, x6, x4, ne",
Expand All @@ -297,9 +297,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eor w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w20, w6, w4, ne",
Expand All @@ -311,9 +311,9 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eor w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w4, w6, w4, ne",
Expand All @@ -324,9 +324,9 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eor w20, w20, w20, lsr #1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel x4, x6, x4, ne",
Expand Down Expand Up @@ -505,21 +505,21 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"and w20, w20, #0x1",
"bfxil x4, x20, #0, #8"
]
},
"setnp al": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eor w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"and w20, w20, #0x1",
"bfxil x4, x20, #0, #8"
]
},
Expand Down
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