Hardware-Matrix-Multiplication-Accelerator

Hardware Matrix Multiplication Accelerator (Verilog RTL)

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Block.sv		Block.sv
Makefile		Makefile
MatMat.sv		MatMat.sv
MatMult.sv		MatMult.sv
Mem.sv		Mem.sv
README.md		README.md
SimWrapper.sv		SimWrapper.sv
modelsim.tcl		modelsim.tcl
tb.sv		tb.sv
wave.do		wave.do

Provide feedback