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Rename simple_node class to SimpleNode (phate#689)
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@phate
phate authored Dec 19, 2024
1 parent 24cfa78 commit dd6f2ba
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Showing 79 changed files with 440 additions and 462 deletions.
62 changes: 31 additions & 31 deletions jlm/hls/backend/rhls2firrtl/RhlsToFirrtlConverter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ namespace jlm::hls

// Handles nodes with 2 inputs and 1 output
circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenSimpleNode(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenSimpleNode(const jlm::rvsdg::SimpleNode * node)
{
// Only handles nodes with a single output
if (node->noutputs() != 1)
Expand Down Expand Up @@ -385,7 +385,7 @@ RhlsToFirrtlConverter::MlirGenSimpleNode(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenSink(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenSink(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand All @@ -410,7 +410,7 @@ RhlsToFirrtlConverter::MlirGenSink(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenLoopConstBuffer(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenLoopConstBuffer(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -465,7 +465,7 @@ RhlsToFirrtlConverter::MlirGenLoopConstBuffer(const jlm::rvsdg::simple_node * no
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenFork(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenFork(const jlm::rvsdg::SimpleNode * node)
{
auto op = dynamic_cast<const jlm::hls::fork_op *>(&node->GetOperation());
bool isConstant = op->IsConstant();
Expand Down Expand Up @@ -567,7 +567,7 @@ RhlsToFirrtlConverter::MlirGenFork(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenStateGate(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenStateGate(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -659,7 +659,7 @@ RhlsToFirrtlConverter::MlirGenStateGate(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsMemResp(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsMemResp(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, false);
Expand Down Expand Up @@ -740,7 +740,7 @@ RhlsToFirrtlConverter::MlirGenHlsMemResp(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsMemReq(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsMemReq(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, false);
Expand Down Expand Up @@ -902,7 +902,7 @@ RhlsToFirrtlConverter::MlirGenHlsMemReq(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsLoad(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsLoad(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, false);
Expand Down Expand Up @@ -1077,7 +1077,7 @@ RhlsToFirrtlConverter::MlirGenHlsLoad(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsDLoad(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsDLoad(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, false);
Expand Down Expand Up @@ -1124,7 +1124,7 @@ RhlsToFirrtlConverter::MlirGenHlsDLoad(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsLocalMem(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsLocalMem(const jlm::rvsdg::SimpleNode * node)
{
auto lmem_op = dynamic_cast<const local_mem_op *>(&(node->GetOperation()));
JLM_ASSERT(lmem_op);
Expand Down Expand Up @@ -1333,7 +1333,7 @@ RhlsToFirrtlConverter::MlirGenHlsLocalMem(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenHlsStore(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenHlsStore(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, false);
Expand Down Expand Up @@ -1477,7 +1477,7 @@ RhlsToFirrtlConverter::MlirGenHlsStore(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenMem(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenMem(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node, true);
Expand Down Expand Up @@ -1694,7 +1694,7 @@ RhlsToFirrtlConverter::MlirGenMem(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenTrigger(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenTrigger(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -1728,7 +1728,7 @@ RhlsToFirrtlConverter::MlirGenTrigger(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenPrint(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenPrint(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -1763,7 +1763,7 @@ RhlsToFirrtlConverter::MlirGenPrint(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenPredicationBuffer(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenPredicationBuffer(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -1828,7 +1828,7 @@ RhlsToFirrtlConverter::MlirGenPredicationBuffer(const jlm::rvsdg::simple_node *
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenBuffer(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenBuffer(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -1968,7 +1968,7 @@ RhlsToFirrtlConverter::MlirGenBuffer(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenAddrQueue(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenAddrQueue(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -2136,7 +2136,7 @@ RhlsToFirrtlConverter::MlirGenAddrQueue(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenDMux(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenDMux(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -2275,7 +2275,7 @@ RhlsToFirrtlConverter::MlirGenDMux(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenNDMux(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenNDMux(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -2322,7 +2322,7 @@ RhlsToFirrtlConverter::MlirGenNDMux(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGenBranch(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGenBranch(const jlm::rvsdg::SimpleNode * node)
{
// Create the module and its input/output ports
auto module = nodeToModule(node);
Expand Down Expand Up @@ -2369,7 +2369,7 @@ RhlsToFirrtlConverter::MlirGenBranch(const jlm::rvsdg::simple_node * node)
}

circt::firrtl::FModuleOp
RhlsToFirrtlConverter::MlirGen(const jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::MlirGen(const jlm::rvsdg::SimpleNode * node)
{
if (dynamic_cast<const hls::sink_op *>(&(node->GetOperation())))
{
Expand Down Expand Up @@ -2468,7 +2468,7 @@ RhlsToFirrtlConverter::MlirGen(const jlm::rvsdg::simple_node * node)
return MlirGenSimpleNode(node);
}

std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp>
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp>
RhlsToFirrtlConverter::MlirGen(
hls::loop_node * loopNode,
mlir::Block * body,
Expand Down Expand Up @@ -2571,7 +2571,7 @@ RhlsToFirrtlConverter::MlirGen(rvsdg::Region * subRegion, mlir::Block * circuitB
auto body = module.getBodyBlock();

// First we create and instantiate all the modules and keep them in a dictionary
std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp> instances =
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp> instances =
createInstances(subRegion, circuitBody, body);
// Wire up the instances
for (const auto & instance : instances)
Expand Down Expand Up @@ -2620,7 +2620,7 @@ RhlsToFirrtlConverter::MlirGen(rvsdg::Region * subRegion, mlir::Block * circuitB
{
// Connect directly to mem
auto mem_out = dynamic_cast<jlm::rvsdg::node_output *>(source->input(0)->origin());
auto sourceNode = instances[dynamic_cast<jlm::rvsdg::simple_node *>(mem_out->node())];
auto sourceNode = instances[dynamic_cast<jlm::rvsdg::SimpleNode *>(mem_out->node())];
auto sourcePort = GetInstancePort(sourceNode, "o" + std::to_string(o->index()));
auto sinkPort = sinkNode->getResult(i + 2);
Connect(body, sinkPort, sourcePort);
Expand Down Expand Up @@ -2712,7 +2712,7 @@ RhlsToFirrtlConverter::MlirGen(rvsdg::Region * subRegion, mlir::Block * circuitB
throw std::logic_error("Unsupported output");
}
// Get the node of the output
jlm::rvsdg::simple_node * source = output->node();
jlm::rvsdg::SimpleNode * source = output->node();
// Get the corresponding InstanceOp
auto sourceNode = instances[source];
// Calculate the result port of the instance:
Expand All @@ -2736,7 +2736,7 @@ RhlsToFirrtlConverter::MlirGen(rvsdg::Region * subRegion, mlir::Block * circuitB
return module;
}

std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp>
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp>
RhlsToFirrtlConverter::createInstances(
rvsdg::Region * subRegion,
mlir::Block * circuitBody,
Expand All @@ -2745,10 +2745,10 @@ RhlsToFirrtlConverter::createInstances(
// create and instantiate all the modules and keep them in a dictionary
auto clock = body->getArgument(0);
auto reset = body->getArgument(1);
std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp> instances;
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp> instances;
for (const auto node : jlm::rvsdg::topdown_traverser(subRegion))
{
if (auto sn = dynamic_cast<jlm::rvsdg::simple_node *>(node))
if (auto sn = dynamic_cast<jlm::rvsdg::SimpleNode *>(node))
{
if (dynamic_cast<const local_mem_req_op *>(&(node->GetOperation()))
|| dynamic_cast<const local_mem_resp_op *>(&(node->GetOperation())))
Expand Down Expand Up @@ -3728,7 +3728,7 @@ RhlsToFirrtlConverter::check_module(circt::firrtl::FModuleOp & module)
}

circt::firrtl::InstanceOp
RhlsToFirrtlConverter::AddInstanceOp(mlir::Block * body, jlm::rvsdg::simple_node * node)
RhlsToFirrtlConverter::AddInstanceOp(mlir::Block * body, jlm::rvsdg::SimpleNode * node)
{
auto name = GetModuleName(node);
// Check if the module has already been instantiated else we need to generate it
Expand Down Expand Up @@ -3855,11 +3855,11 @@ RhlsToFirrtlConverter::InitializeMemReq(circt::firrtl::FModuleOp module)
Connect(body, memWidth, invalid3);
}

// Takes a jlm::rvsdg::simple_node and creates a firrtl module with an input
// Takes a jlm::rvsdg::SimpleNode and creates a firrtl module with an input
// bundle for each node input and output bundle for each node output
// Returns a circt::firrtl::FModuleOp with an empty body
circt::firrtl::FModuleOp
RhlsToFirrtlConverter::nodeToModule(const jlm::rvsdg::simple_node * node, bool mem)
RhlsToFirrtlConverter::nodeToModule(const jlm::rvsdg::SimpleNode * node, bool mem)
{
// Generate a vector with all inputs and outputs of the module
::llvm::SmallVector<circt::firrtl::PortInfo> ports;
Expand Down
50 changes: 25 additions & 25 deletions jlm/hls/backend/rhls2firrtl/RhlsToFirrtlConverter.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -104,65 +104,65 @@ class RhlsToFirrtlConverter : public BaseHLS

std::unordered_map<std::string, circt::firrtl::FModuleOp> modules;
// FIRRTL generating functions
std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp>
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp>
MlirGen(hls::loop_node * loopNode, mlir::Block * body, mlir::Block * circuitBody);
circt::firrtl::FModuleOp
MlirGen(rvsdg::Region * subRegion, mlir::Block * circuitBody);
circt::firrtl::FModuleOp
MlirGen(const jlm::rvsdg::simple_node * node);
MlirGen(const jlm::rvsdg::SimpleNode * node);
// Operations
circt::firrtl::FModuleOp
MlirGenSink(const jlm::rvsdg::simple_node * node);
MlirGenSink(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenLoopConstBuffer(const jlm::rvsdg::simple_node * node);
MlirGenLoopConstBuffer(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenFork(const jlm::rvsdg::simple_node * node);
MlirGenFork(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenStateGate(const jlm::rvsdg::simple_node * node);
MlirGenStateGate(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenMem(const jlm::rvsdg::simple_node * node);
MlirGenMem(const jlm::rvsdg::SimpleNode * node);
/**
* Generate a FIRRTL module for a HLS memory response node that implements the functionality for
* retreiving memory responses.
* @param node The HLS memory response node.
* @return The generated FIRRTL module.
*/
circt::firrtl::FModuleOp
MlirGenHlsMemResp(const jlm::rvsdg::simple_node * node);
MlirGenHlsMemResp(const jlm::rvsdg::SimpleNode * node);
/**
* Generate a FIRRTL module for a HLS memory request node that implements the functionality for
* performing memory requests.
* @param node The HLS memory request node.
* @return The generated FIRRTL module.
*/
circt::firrtl::FModuleOp
MlirGenHlsMemReq(const jlm::rvsdg::simple_node * node);
MlirGenHlsMemReq(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenHlsLoad(const jlm::rvsdg::simple_node * node);
MlirGenHlsLoad(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenHlsDLoad(const jlm::rvsdg::simple_node * node);
MlirGenHlsDLoad(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenHlsLocalMem(const jlm::rvsdg::simple_node * node);
MlirGenHlsLocalMem(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenHlsStore(const jlm::rvsdg::simple_node * node);
MlirGenHlsStore(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenTrigger(const jlm::rvsdg::simple_node * node);
MlirGenTrigger(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenPrint(const jlm::rvsdg::simple_node * node);
MlirGenPrint(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenAddrQueue(const jlm::rvsdg::simple_node * node);
MlirGenAddrQueue(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenPredicationBuffer(const jlm::rvsdg::simple_node * node);
MlirGenPredicationBuffer(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenBuffer(const jlm::rvsdg::simple_node * node);
MlirGenBuffer(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenDMux(const jlm::rvsdg::simple_node * node);
MlirGenDMux(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenNDMux(const jlm::rvsdg::simple_node * node);
MlirGenNDMux(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenBranch(const jlm::rvsdg::simple_node * node);
MlirGenBranch(const jlm::rvsdg::SimpleNode * node);
circt::firrtl::FModuleOp
MlirGenSimpleNode(const jlm::rvsdg::simple_node * node);
MlirGenSimpleNode(const jlm::rvsdg::SimpleNode * node);

// Helper functions
void
Expand Down Expand Up @@ -247,7 +247,7 @@ class RhlsToFirrtlConverter : public BaseHLS
circt::firrtl::WhenOp
AddWhenOp(mlir::Block * body, mlir::Value condition, bool elseStatment);
circt::firrtl::InstanceOp
AddInstanceOp(mlir::Block * body, jlm::rvsdg::simple_node * node);
AddInstanceOp(mlir::Block * body, jlm::rvsdg::SimpleNode * node);
circt::firrtl::ConstantOp
GetConstant(mlir::Block * body, int size, int value);
circt::firrtl::InvalidValueOp
Expand All @@ -274,7 +274,7 @@ class RhlsToFirrtlConverter : public BaseHLS
mlir::BlockArgument
GetResetSignal(circt::firrtl::FModuleOp module);
circt::firrtl::FModuleOp
nodeToModule(const jlm::rvsdg::simple_node * node, bool mem = false);
nodeToModule(const jlm::rvsdg::SimpleNode * node, bool mem = false);
circt::firrtl::IntType
GetIntType(int size);
circt::firrtl::IntType
Expand All @@ -286,7 +286,7 @@ class RhlsToFirrtlConverter : public BaseHLS
bool
IsIdentityMapping(const jlm::rvsdg::match_op & op);

std::unordered_map<jlm::rvsdg::simple_node *, circt::firrtl::InstanceOp>
std::unordered_map<jlm::rvsdg::SimpleNode *, circt::firrtl::InstanceOp>
createInstances(rvsdg::Region * subRegion, mlir::Block * circuitBody, mlir::Block * body);
void
check_module(circt::firrtl::FModuleOp & module);
Expand Down
2 changes: 1 addition & 1 deletion jlm/hls/backend/rhls2firrtl/base-hls.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -140,7 +140,7 @@ BaseHLS::create_node_names(rvsdg::Region * r)
{
for (auto & node : r->Nodes())
{
if (dynamic_cast<jlm::rvsdg::simple_node *>(&node))
if (dynamic_cast<jlm::rvsdg::SimpleNode *>(&node))
{
get_node_name(&node);
}
Expand Down
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