i#4881: Fix LRU counter bug in drcachesim

clients/drcachesim/simulator/cache_lru.cpp

@@ -37,6 +37,31 @@
 // The count value 0 means the most recent access, and the cache line with the
 // highest counter value will be picked for replacement in replace_which_way.
 
+bool
+cache_lru_t::init(int associativity, int block_size, int total_size,
+                  caching_device_t *parent, caching_device_stats_t *stats,
+                  prefetcher_t *prefetcher, bool inclusive, bool coherent_cache, int id,
+                  snoop_filter_t *snoop_filter,
+                  const std::vector<caching_device_t *> &children)
+{
+    // Works in the same way as the base class,
+    // except that the counters are initialized in a different way.
+
+    bool ret_val =
+        cache_t::init(associativity, block_size, total_size, parent, stats, prefetcher,
+                      inclusive, coherent_cache, id, snoop_filter, children);
+    if (ret_val == false)
+        return false;
+
+    // Initialize line counters with 0, 1, 2, ..., associativity - 1.
+    for (int i = 0; i < blocks_per_set_; i++) {
+        for (int way = 0; way < associativity_; ++way) {
+            get_caching_device_block(i << assoc_bits_, way).counter_ = way;
+        }
+    }
+    return true;
+}
+
 void
 cache_lru_t::access_update(int line_idx, int way)
 {
@@ -69,7 +94,5 @@ cache_lru_t::replace_which_way(int line_idx)
             max_way = way;
         }
     }
-    // Set to non-zero for later access_update optimization on repeated access
-    get_caching_device_block(line_idx, max_way).counter_ = 1;
     return max_way;
 }

clients/drcachesim/simulator/cache_lru.h

@@ -39,6 +39,14 @@
 #include "cache.h"
 
 class cache_lru_t : public cache_t {
+public:
+    bool
+    init(int associativity, int line_size, int total_size, caching_device_t *parent,
+         caching_device_stats_t *stats, prefetcher_t *prefetcher, bool inclusive = false,
+         bool coherent_cache = false, int id_ = -1,
+         snoop_filter_t *snoop_filter_ = nullptr,
+         const std::vector<caching_device_t *> &children = {}) override;
+
 protected:
     void
     access_update(int line_idx, int way) override;

clients/drcachesim/tests/offline-legacy.templatex

@@ -1,17 +1,17 @@
 Cache simulation results:
 Core #0 \(1 thread\(s\)\)
   L1I stats:
-    Hits:                         *61,?531
-    Misses:                            731
+    Hits:                         *61,?538
+    Misses:                            724
     Invalidations:                       0
-    Miss rate:                        1[,\.]?17%
+    Miss rate:                        1[,\.]?16%
   L1D stats:
-    Hits:                         *21,?155
-    Misses:                            808
+    Hits:                         *21,?189
+    Misses:                            774
     Invalidations:                       0
-    Prefetch hits:                     182
-    Prefetch misses:                   626
-    Miss rate:                        3[,\.]?68%
+    Prefetch hits:                     151
+    Prefetch misses:                   623
+    Miss rate:                        3[,\.]?52%
 Core #1 \(4 thread\(s\)\)
   L1I stats:
     Hits:                         *19,?428
@@ -28,11 +28,11 @@ Core #1 \(4 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
-    Hits:                              385
-    Misses:                        *1,?542
+    Hits:                              342
+    Misses:                        *1,?544
     Invalidations:                       0
-    Prefetch hits:                     143
-    Prefetch misses:                   675
-    Local miss rate:                 80[,\.]?02%
-    Child hits:                  *122,?839
+    Prefetch hits:                     141
+    Prefetch misses:                   674
+    Local miss rate:                 81[,\.]?87%
+    Child hits:                  *122,?849
     Total miss rate:                  1[,\.]?24%

clients/drcachesim/tests/offline-snappy-serial.templatex

@@ -1,5 +1,5 @@
 Cache simulation results:
 .*
 LL stats:
-    Hits:                           58,699
+    Hits:                           78,312
 .*