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Move Psapi dependency out of core library
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@M3m3M4n
M3m3M4n committed Jul 23, 2021
1 parent 1ce3e57 commit b5c528a
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Showing 28 changed files with 2,735 additions and 462 deletions.
4 changes: 2 additions & 2 deletions core/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -333,9 +333,9 @@ endif (WIN32)
_DR_get_static_libc_list(static_libc_list)
if (WIN32)
if (DEBUG)
set(WIN32_C_LIB libcmtd Psapi)
set(WIN32_C_LIB libcmtd)
else (DEBUG)
set(WIN32_C_LIB libcmt Psapi)
set(WIN32_C_LIB libcmt)
endif (DEBUG)
set(NOLIBC_DLL_ENTRY /entry:DllMain)
endif ()
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11 changes: 9 additions & 2 deletions core/heap.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1901,8 +1901,15 @@ vmm_heap_init()
if (DYNAMO_OPTION(vm_reserve)) {
vmm_heap_unit_init(&heapmgt->vmcode, DYNAMO_OPTION(vm_size), true, "vmcode");
if (!REACHABLE_HEAP()) {
vmm_heap_unit_init(&heapmgt->vmheap, DYNAMO_OPTION(vmheap_size), false,
"vmheap");
vmm_heap_unit_init(
&heapmgt->vmheap,
/* Use vmheap_size_wow64 if target is WoW64 windows process. */
IF_WINDOWS_ELSE(IF_X64_ELSE(is_wow64_process(NT_CURRENT_PROCESS)
? DYNAMO_OPTION(vmheap_size_wow64)
: DYNAMO_OPTION(vmheap_size),
DYNAMO_OPTION(vmheap_size)),
DYNAMO_OPTION(vmheap_size)),
false, "vmheap");
}
}
}
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42 changes: 42 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1255,6 +1255,20 @@ encode_opnd_prfop(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out
return encode_opnd_int(0, 5, false, 0, 0, opnd, enc_out);
}

/* op2: 3-bit immediate from bits 5-7 */

static inline bool
decode_opnd_op2(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_opnd_int(5, 3, false, 0, OPSZ_3b, 0, enc, opnd);
}

static inline bool
encode_opnd_op2(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_int(5, 3, false, 0, 0, opnd, enc_out);
}

/* w5: W register or WZR at bit position 5 */

static inline bool
Expand Down Expand Up @@ -1608,6 +1622,20 @@ encode_opnd_cmode3(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_ou
return encode_opnd_int(13, 3, false, false, 0, opnd, enc_out);
}

/* crn: 4-bit immediate from bits 12-15*/

static inline bool
decode_opnd_crn(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_opnd_int(12, 4, false, 0, OPSZ_4b, 0, enc, opnd);
}

static inline bool
encode_opnd_crn(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_int(12, 4, false, 0, 0, opnd, enc_out);
}

/* cond: condition operand for conditional compare */

static inline bool
Expand Down Expand Up @@ -1651,6 +1679,20 @@ encode_opnd_scale(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out
return true;
}

/* op1: 3-bit immediate from bits 16-18 */

static inline bool
decode_opnd_op1(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_opnd_int(16, 3, false, 0, OPSZ_3b, 0, enc, opnd);
}

static inline bool
encode_opnd_op1(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_int(16, 3, false, 0, 0, opnd, enc_out);
}

/* fpimm8: immediate operand for SIMD fmov */

static inline bool
Expand Down
116 changes: 115 additions & 1 deletion core/ir/aarch64/codec.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@
---------------------------xxxxx q0p2 # Q register, add 2
---------------------------xxxxx q0p3 # Q register, add 3
---------------------------xxxxx prfop # prefetch operation
------------------------xxx----- op2 # 3 bit immediate from 5-7
----------------------xxxxx----- w5 # W register (or WZR)
----------------------xxxxx----- x5 # X register (or XZR)
----------------------xxxxx----- x5sp # X register or XSP
Expand All @@ -99,8 +100,10 @@
-----------------xxxxx---------- q10 # Q register
----------------xxx------------- ext # extend type
----------------xxx------------- cmode3 # immediate from 13-15
----------------xxxx------------ crn # 4 bit immediate from 12-15
----------------xxxx------------ cond # condition for CCMN, CCMP
----------------xxxxxx---------- scale # encoding of #fbits value in scale field
-------------xxx---------------- op1 # 3 bit immediate from 16-18
-------------xxx------xxxxx----- fpimm8 # floating-point immediate for vector fmov
-------------xxx------xxxxx----- imm8 # immediate from 16:18 and 5:9
-------------xxxxxxxxxxxxxx----- sysops # immediate operands for SYS
Expand Down Expand Up @@ -1433,7 +1436,6 @@ x001111001000010xxxxxxxxxxxxxxxx scvtf d0 : wx5 scale
0x001110xx100000001010xxxxxxxxxx saddlp dq0 : dq5 bhsd_sz
0000111100xxxxxx101001xxxxxxxxxx sshll d0 : d5 immhb
0100111100xxxxxx101001xxxxxxxxxx sshll2 q0 : q5 immhb

01011110000xxxxx000000xxxxxxxxxx sha1c q0 : s5 d16
0101111000101000000010xxxxxxxxxx sha1h s0 : s5
01011110000xxxxx001000xxxxxxxxxx sha1m q0 : s5 d16
Expand All @@ -1458,3 +1460,115 @@ x001111001000010xxxxxxxxxxxxxxxx scvtf d0 : wx5 scale
0x001110xx0xxxxx010110xxxxxxxxxx uzp2 dq0 : dq5 dq16 bhsd_sz
00001110xx100001001010xxxxxxxxxx xtn d0 : d5 bhsd_sz
01001110xx100001001010xxxxxxxxxx xtn2 q0 : q5 bhsd_sz
0101111101xxxxxx001001xxxxxxxxxx srshr d0 : d5 immhb
0x0011110xxxxxxx001001xxxxxxxxxx srshr dq0 : dq5 sd_sz immhb
0101111101xxxxxx001101xxxxxxxxxx srsra d0 : d5 immhb
0101111101xxxxxx000001xxxxxxxxxx sshr d0 : d5 immhb
0x0011110xxxxxxx000001xxxxxxxxxx sshr dq0 : dq5 sd_sz immhb
0101111101xxxxxx000101xxxxxxxxxx ssra d0 : d5 immhb
0101111101xxxxxx010101xxxxxxxxxx shl d0 : d5 immhb
0111111101xxxxxx010101xxxxxxxxxx sli d0 : d5 immhb
0111111101xxxxxx000001xxxxxxxxxx ushr d0 : d5 immhb
0x1011110xxxxxxx000001xxxxxxxxxx ushr dq0 : dq5 sd_sz immhb
0111111101xxxxxx000101xxxxxxxxxx usra d0 : d5 immhb
0000111100xxxxxx100001xxxxxxxxxx shrn d0 : d5 immhb
0100111100xxxxxx100001xxxxxxxxxx shrn2 q0 : q5 immhb
00101110xx100001001110xxxxxxxxxx shll d0 : d5 bhs_sz
01101110xx100001001110xxxxxxxxxx shll2 q0 : q5 bhs_sz
x001111011110001000000xxxxxxxxxx fcvtmu wx0 : h5
x001111000110001000000xxxxxxxxxx fcvtmu wx0 : s5
x001111001110001000000xxxxxxxxxx fcvtmu wx0 : d5
0111111001111001101110xxxxxxxxxx fcvtmu h0 : h5
0111111000100001101110xxxxxxxxxx fcvtmu s0 : s5
0111111001100001101110xxxxxxxxxx fcvtmu d0 : d5
0x1011100x100001101110xxxxxxxxxx fcvtmu dq0 : dq5 sd_sz
x001111011100001000000xxxxxxxxxx fcvtnu wx0 : h5
x001111000100001000000xxxxxxxxxx fcvtnu wx0 : s5
x001111001100001000000xxxxxxxxxx fcvtnu wx0 : d5
0111111001111001101010xxxxxxxxxx fcvtnu h0 : h5
0111111000100001101010xxxxxxxxxx fcvtnu s0 : s5
0111111001100001101010xxxxxxxxxx fcvtnu d0 : d5
0x1011100x100001101010xxxxxxxxxx fcvtnu dq0 : dq5 sd_sz
0101111011100000101010xxxxxxxxxx cmlt d0 : d5
0x001110xx100000101010xxxxxxxxxx cmlt dq0 : dq5 bhsd_sz
1101010100101xxxxxxxxxxxxxxxxxxx sysl x0 : op1 crn imm4 op2
11010100101xxxxxxxxxxxxxxxx00001 dcps1 : imm16
11010100101xxxxxxxxxxxxxxxx00010 dcps2 : imm16
11010100101xxxxxxxxxxxxxxxx00011 dcps3 : imm16
11010110101111110000001111100000 drps :
11010110100111110000001111100000 eret :
0101111000100000001110xxxxxxxxxx suqadd b0 : b5
0101111001100000001110xxxxxxxxxx suqadd h0 : h5
0101111010100000001110xxxxxxxxxx suqadd s0 : s5
0101111011100000001110xxxxxxxxxx suqadd d0 : d5
0x001110xx100000001110xxxxxxxxxx suqadd dq0 : dq5 bhsd_sz
0x001110000xxxxx0xx100xxxxxxxxxx tbx dq0 : dq5 dq16 len
0010111100xxxxxx100111xxxxxxxxxx uqrshrn d0 : d5 immhb
0110111100xxxxxx100111xxxxxxxxxx uqrshrn2 q0 : q5 immhb
0x0011101x100001110010xxxxxxxxxx urecpe dq0 : dq5 sd_sz
0111111101xxxxxx001101xxxxxxxxxx ursra d0 : d5 immhb
0111111000100000001110xxxxxxxxxx usqadd b0 : b5
0111111001100000001110xxxxxxxxxx usqadd h0 : h5
0111111010100000001110xxxxxxxxxx usqadd s0 : s5
0111111011100000001110xxxxxxxxxx usqadd d0 : d5
0x101110xx100000001110xxxxxxxxxx usqadd dq0 : dq5 bhsd_sz
0111111000100000011110xxxxxxxxxx sqneg b0 : b5
0111111001100000011110xxxxxxxxxx sqneg h0 : h5
0111111010100000011110xxxxxxxxxx sqneg s0 : s5
0111111011100000011110xxxxxxxxxx sqneg d0 : d5
0x101110xx100000011110xxxxxxxxxx sqneg dq0 : dq5 bhsd_sz
0000111100xxxxxx100111xxxxxxxxxx sqrshrn d0 : d5 immhb
0100111100xxxxxx100111xxxxxxxxxx sqrshrn2 q0 : q5 immhb
0010111100xxxxxx100011xxxxxxxxxx sqrshrun d0 : d5 immhb
0110111100xxxxxx100011xxxxxxxxxx sqrshrun2 q0 : q5 immhb
0111111100xxxxxx011001xxxxxxxxxx sqshlu s0 : s5 immhb
0111111101xxxxxx011001xxxxxxxxxx sqshlu d0 : d5 immhb
0x1011110xxxxxxx011001xxxxxxxxxx sqshlu dq0 : dq5 sd_sz immhb
0010111100xxxxxx100001xxxxxxxxxx sqshrun d0 : d5 immhb
0110111100xxxxxx100001xxxxxxxxxx sqshrun2 q0 : q5 immhb
0111111101xxxxxx010001xxxxxxxxxx sri d0 : d5 immhb
0x1011110xxxxxxx010001xxxxxxxxxx sri dq0 : dq5 sd_sz immhb
0000111000110000110010xxxxxxxxxx fmaxnmv h0 : d5
0100111000110000110010xxxxxxxxxx fmaxnmv h0 : q5
0110111000110000110010xxxxxxxxxx fmaxnmv s0 : q5
0000111010110000110010xxxxxxxxxx fminnmv h0 : d5
0100111010110000110010xxxxxxxxxx fminnmv h0 : q5
0110111010110000110010xxxxxxxxxx fminnmv s0 : q5
0101111011111001110110xxxxxxxxxx frecpe h0 : h5
0101111010100001110110xxxxxxxxxx frecpe s0 : s5
0101111011100001110110xxxxxxxxxx frecpe d0 : d5
0x0011101x100001110110xxxxxxxxxx frecpe dq0 : dq5 bd_sz
0101111011111001111110xxxxxxxxxx frecpx h0 : h5
0101111010100001111110xxxxxxxxxx frecpx s0 : s5
0101111011100001111110xxxxxxxxxx frecpx d0 : d5
0111111011111001110110xxxxxxxxxx frsqrte h0 : h5
0111111010100001110110xxxxxxxxxx frsqrte s0 : s5
0111111011100001110110xxxxxxxxxx frsqrte d0 : d5
0x1011101x100001110110xxxxxxxxxx frsqrte dq0 : dq5 bd_sz
0000111100xxxxxx100011xxxxxxxxxx rshrn d0 : d5 immhb
0100111100xxxxxx100011xxxxxxxxxx rshrn2 q0 : q5 immhb
0x001110xx110000001110xxxxxxxxxx saddlv dq0 : dq5 bhsd_sz
0101111000100000011110xxxxxxxxxx sqabs b0 : b5
0101111001100000011110xxxxxxxxxx sqabs h0 : h5
0101111010100000011110xxxxxxxxxx sqabs s0 : s5
0101111011100000011110xxxxxxxxxx sqabs d0 : d5
0x001110xx100000011110xxxxxxxxxx sqabs dq0 : dq5 bhsd_sz
0111111011100000100110xxxxxxxxxx cmle d0 : d5
0x101110xx100000100110xxxxxxxxxx cmle dq0 : dq5 bhsd_sz
0111111011111000110110xxxxxxxxxx fcmle h0 : h5
0111111010100000110110xxxxxxxxxx fcmle s0 : s5
0111111011100000110110xxxxxxxxxx fcmle d0 : d5
0x1011101x100000110110xxxxxxxxxx fcmle dq0 : dq5 sd_sz
0101111011111000111010xxxxxxxxxx fcmlt h0 : h5
0101111010100000111010xxxxxxxxxx fcmlt s0 : s5
0101111011100000111010xxxxxxxxxx fcmlt d0 : d5
0x0011101x100000111010xxxxxxxxxx fcmlt dq0 : dq5 sd_sz
00011110111xxxxx001000xxxxx10000 fcmpe : h5 h16
0001111011100000001000xxxxx11000 fcmpe : h5
00011110001xxxxx001000xxxxx10000 fcmpe : s5 s16
0001111000100000001000xxxxx11000 fcmpe : s5
00011110011xxxxx001000xxxxx10000 fcmpe : d5 d16
0001111001100000001000xxxxx11000 fcmpe : d5
0111111001100001011010xxxxxxxxxx fcvtxn s0 : d5
0010111001100001011010xxxxxxxxxx fcvtxn d0 : q5
0110111001100001011010xxxxxxxxxx fcvtxn2 q0 : q5
3 changes: 2 additions & 1 deletion core/ir/instr_shared.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3697,7 +3697,8 @@ instr_is_reg_spill_or_restore_ex(void *drcontext, instr_t *instr, bool DR_only,
if (reg == NULL)
reg = &myreg;
if (instr_check_tls_spill_restore(instr, spill, reg, &check_disp)) {
if (!DR_only ||
/* We do not want to count an mcontext base load as a reg spill/restore. */
if ((!DR_only && check_disp != os_tls_offset((ushort)TLS_DCONTEXT_SLOT)) ||
(reg_spill_tls_offs(*reg) != -1 &&
/* Mangling may choose to spill registers to a not natural tls offset,
* e.g. rip-rel mangling will, if rax is used by the instruction. We
Expand Down
4 changes: 4 additions & 0 deletions core/lib/dr_inject.h
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Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,10 @@ DR_EXPORT
*
* \param[in] pid PID for process to attach.
*
* \param[in] appname The path to the target executable. The caller
* must ensure this data is valid until the
* inject data is disposed.
*
* \param[out] data An opaque pointer that should be passed to
* subsequent dr_inject_* routines to refer to
* this process.
Expand Down
9 changes: 8 additions & 1 deletion core/optionsx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1595,7 +1595,14 @@ OPTION_DEFAULT(uint_size, vmheap_size, IF_X64_ELSE(8192ULL, 128) * 1024 * 1024,
* for which we need more than 256MB.
*/
"capacity of virtual memory region reserved for unreachable heap")

#ifdef WINDOWS
OPTION_DEFAULT(uint_size, vmheap_size_wow64, 128 * 1024 * 1024,
/* XXX: default value is currently not good enough for 32-bit sqlserver,
* for which we need more than 256MB.
*/
"capacity of virtual memory region reserved for unreachable heap "
"on WoW64 processes")
#endif
/* We hardcode an address in the mmap_text region here, but verify via
* in vmk_init().
* For Linux we start higher to avoid limiting the brk (i#766), but with our
Expand Down
2 changes: 1 addition & 1 deletion core/unix/injector.c
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Original file line number Diff line number Diff line change
Expand Up @@ -789,7 +789,7 @@ dr_inject_wait_for_child(void *data, uint64 timeout_millis)
else {
int exit = 0;
struct timespec t;
t.tv_sec = 1;
t.tv_sec = 1;
t.tv_nsec = 0L;
do {
/* At this point dr_inject_process_run has called PTRACE_DETACH
Expand Down
68 changes: 44 additions & 24 deletions core/unix/signal.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2367,6 +2367,28 @@ handle_sigsuspend(dcontext_t *dcontext, kernel_sigset_t *set, size_t sigsetsize)
#endif
}

static void
terminate_sigsuspend(dcontext_t *dcontext, thread_sig_info_t *info,
kernel_ucontext_t *ucxt)
{
ASSERT(info->in_sigsuspend);
/* Sigsuspend ends when a signal is received, so restore the
* old blocked set.
*/
info->app_sigblocked = info->app_sigblocked_save;
info->in_sigsuspend = false;
/* Update the set to restore to post-signal-delivery. */
#ifdef MACOS
ucxt->uc_sigmask = *(__darwin_sigset_t *)&info->app_sigblocked;
#else
ucxt->uc_sigmask = info->app_sigblocked;
#endif
DOLOG(3, LOG_ASYNCH, {
LOG(THREAD, LOG_ASYNCH, 3, "after sigsuspend, blocked signals are now:\n");
dump_sigset(dcontext, &info->app_sigblocked);
});
}

/**** utility routines ***********************************************/
#ifdef DEBUG
static void
Expand Down Expand Up @@ -4295,26 +4317,6 @@ record_pending_signal(dcontext_t *dcontext, int sig, kernel_ucontext_t *ucxt,
if (kernel_sigismember(&info->app_sigblocked, sig))
blocked = true;

if (info->in_sigsuspend) {
/* sigsuspend ends when a signal is received, so restore the
* old blocked set
*/
info->app_sigblocked = info->app_sigblocked_save;
info->in_sigsuspend = false;
/* update the set to restore to post-signal-delivery */
#ifdef MACOS
ucxt->uc_sigmask = *(__darwin_sigset_t *)&info->app_sigblocked;
#else
ucxt->uc_sigmask = info->app_sigblocked;
#endif
#ifdef DEBUG
if (d_r_stats->loglevel >= 3 && (d_r_stats->logmask & LOG_ASYNCH) != 0) {
LOG(THREAD, LOG_ASYNCH, 3, "after sigsuspend, blocked signals are now:\n");
dump_sigset(dcontext, &info->app_sigblocked);
}
#endif
}

if (get_at_syscall(dcontext))
syslen = syscall_instr_length(dr_get_isa_mode(dcontext));

Expand Down Expand Up @@ -4662,7 +4664,7 @@ record_pending_signal(dcontext_t *dcontext, int sig, kernel_ucontext_t *ucxt,

pend->next = info->sigpending[sig];
info->sigpending[sig] = pend;
pend->unblocked = !blocked;
pend->unblocked_at_receipt = !blocked;

/* FIXME: note that for asynchronous signals we don't need to
* bother to record exact machine context, even entire frame,
Expand Down Expand Up @@ -5576,6 +5578,9 @@ execute_handler_from_cache(dcontext_t *dcontext, int sig, sigframe_rt_t *our_fra

LOG(THREAD, LOG_ASYNCH, 3, "\txsp is " PFX "\n", xsp);

if (info->in_sigsuspend)
terminate_sigsuspend(dcontext, info, uc);

/* copy frame to appropriate stack and convert to non-rt if necessary */
copy_frame_to_stack(dcontext, info, sig, our_frame, (void *)xsp, false /*!pending*/);
LOG(THREAD, LOG_ASYNCH, 3, "\tcopied frame from " PFX " to " PFX "\n", our_frame,
Expand Down Expand Up @@ -5790,6 +5795,9 @@ execute_handler_from_dispatch(dcontext_t *dcontext, int sig)
}
CLIENT_ASSERT(action == DR_SIGNAL_DELIVER, "invalid signal event return value");

if (info->in_sigsuspend)
terminate_sigsuspend(dcontext, info, uc);

/* now that we've made all our changes and given the client a
* chance to make changes, copy the frame to the appropriate stack
* location and convert to non-rt if necessary
Expand Down Expand Up @@ -6387,10 +6395,17 @@ receive_pending_signal(dcontext_t *dcontext)
for (sig = 1; sig <= MAX_SIGNUM; sig++) {
if (info->sigpending[sig] != NULL) {
bool executing = true;
/* We do not re-check whether blocked if it was unblocked at
* receive time, to properly handle sigsuspend (i#1340).
/* We do not re-check whether blocked if it was unblocked at receive time
* to handle a signal arriving during a mask-changing syscall
* (handle_pre_extended_syscall_sigmasks()). The problem is that we exit
* the syscall (restoring the pre-syscall mask) *before* we come here.
* We clear the unblocked_at_receipt field below to limit this to the
* first syscall, to avoid erroneously delivering more later (xref
* i#4998). We don't need this for sigsuspend because we can delay its
* post-syscall mask restore until signal delivery
* (terminate_sigsuspend()).
*/
if (!info->sigpending[sig]->unblocked &&
if (!info->sigpending[sig]->unblocked_at_receipt &&
kernel_sigismember(&info->app_sigblocked, sig)) {
LOG(THREAD, LOG_ASYNCH, 3, "\tsignal %d is blocked!\n", sig);
continue;
Expand All @@ -6416,6 +6431,11 @@ receive_pending_signal(dcontext_t *dcontext)
}
}
}
/* Only one signal can be delivered ignoring the back-in-dispatch blocked set. */
for (sig = 1; sig <= MAX_SIGNUM; sig++) {
if (info->sigpending[sig] != NULL && info->sigpending[sig]->unblocked_at_receipt)
info->sigpending[sig]->unblocked_at_receipt = false;
}
/* barrier to prevent compiler from moving the below write above the loop */
__asm__ __volatile__("" : : : "memory");
info->accessing_sigpending = false;
Expand Down
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