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i#3044 AArch64 SVE codec: Add MOV, MOVS, PFALSE, PFIRST, PTRUE, PTRUE…
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…S, SEL (#5818)

This patch adds the appropriate macros, tests and codec entries
to encode the following variants:
PFALSE  <Pd>.B
PFIRST  <Pdn>.B, <Pg>, <Pdn>.B
SEL     <Pd>.B, <Pg>, <Pn>.B, <Pm>.B
SEL     <Zd>.<Ts>, <Pv>, <Zn>.<Ts>, <Zm>.<Ts>
MOV     <Pd>.B, <Pn>.B
MOVS    <Pd>.B, <Pg>/Z, <Pn>.B
PTRUE   <Pd>.<Ts>{, <pattern>}
PTRUES  <Pd>.<Ts>{, <pattern>}

Issue #3044
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@cmannett85-arm @dolanzhao
cmannett85-arm authored and dolanzhao committed Jan 30, 2023
1 parent 4621833 commit 63c8f87
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Showing 6 changed files with 758 additions and 8 deletions.
17 changes: 17 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2048,6 +2048,23 @@ encode_opnd_p_b_5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out
return encode_single_sized(OPSZ_SCALABLE_PRED, 5, BYTE_REG, opnd, enc_out);
}

/* p5: P register */

static inline bool
decode_opnd_p5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
*opnd = opnd_create_reg(DR_REG_P0 + extract_uint(enc, 5, 4));
return true;
}

static inline bool
encode_opnd_p5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
if (!opnd_is_predicate_reg(opnd))
return false;
return encode_opnd_p(5, 15, opnd, enc_out);
}

static inline bool
decode_opnd_p5_zer(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
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22 changes: 14 additions & 8 deletions core/ir/aarch64/codec_sve.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -66,10 +66,10 @@
001001010000xxxx11xxxx0xxxx1xxxx n 875 SVE brkpb p_b_0 : p10_zer p_b_5 p_b_16
001001010100xxxx11xxxx0xxxx1xxxx w 876 SVE brkpbs p_b_0 : p10_zer p_b_5 p_b_16
00000101xx110000101xxxxxxxxxxxxx n 835 SVE clasta wx_size_0_zr : p10_lo wx_size_0_zr z_size_bhsd_5
00000101xx101010100xxxxxxxxxxxxx n 835 SVE clasta bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5
00000101xx101010100xxxxxxxxxxxxx n 835 SVE clasta bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5
00000101xx101000100xxxxxxxxxxxxx n 835 SVE clasta z_size_bhsd_0 : p10_lo z_size_bhsd_0 z_size_bhsd_5
00000101xx110001101xxxxxxxxxxxxx n 836 SVE clastb wx_size_0_zr : p10_lo wx_size_0_zr z_size_bhsd_5
00000101xx101011100xxxxxxxxxxxxx n 836 SVE clastb bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5
00000101xx101011100xxxxxxxxxxxxx n 836 SVE clastb bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5
00000101xx101001100xxxxxxxxxxxxx n 836 SVE clastb z_size_bhsd_0 : p10_lo z_size_bhsd_0 z_size_bhsd_5
00100101xx0xxxxx100xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5
00100100xx0xxxxx001xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16
Expand Down Expand Up @@ -156,10 +156,10 @@
000001001011xxxx110000xxxxxxxxxx n 851 SVE incw z_s_0 : z_s_0 pred_constr mul imm4_16p1
00000101xx100100001110xxxxxxxxxx n 881 SVE insr z_size_bhsd_0 : z_size_bhsd_0 wx_size_5_zr
00000101xx110100001110xxxxxxxxxx n 881 SVE insr z_size_bhsd_0 : z_size_bhsd_0 bhsd_size_reg5
00000101xx100000101xxxxxxxxxxxxx n 837 SVE lasta wx_size_0_zr : p10_lo z_size_bhsd_5
00000101xx100010100xxxxxxxxxxxxx n 837 SVE lasta bhsd_size_reg0 : p10_lo z_size_bhsd_5
00000101xx100001101xxxxxxxxxxxxx n 838 SVE lastb wx_size_0_zr : p10_lo z_size_bhsd_5
00000101xx100011100xxxxxxxxxxxxx n 838 SVE lastb bhsd_size_reg0 : p10_lo z_size_bhsd_5
00000101xx100000101xxxxxxxxxxxxx n 837 SVE lasta wx_size_0_zr : p10_lo z_size_bhsd_5
00000101xx100010100xxxxxxxxxxxxx n 837 SVE lasta bhsd_size_reg0 : p10_lo z_size_bhsd_5
00000101xx100001101xxxxxxxxxxxxx n 838 SVE lastb wx_size_0_zr : p10_lo z_size_bhsd_5
00000101xx100011100xxxxxxxxxxxxx n 838 SVE lastb bhsd_size_reg0 : p10_lo z_size_bhsd_5
1000010110xxxxxx000xxxxxxxx0xxxx n 227 SVE ldr p0 : svemem_gpr_simm9_vl
1000010110xxxxxx010xxxxxxxxxxxxx n 227 SVE ldr z0 : svemem_gpr_simm9_vl
00000100xx0xxxxx110xxxxxxxxxxxxx n 787 SVE mad z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_16 z_size_bhsd_5
Expand All @@ -182,7 +182,11 @@
001001011000xxxx01xxxx0xxxx0xxxx n 327 SVE orr p_b_0 : p10_zer p_b_5 p_b_16
00000100011xxxxx001100xxxxxxxxxx n 327 SVE orr z_d_0 : z_d_5 z_d_16
001001011100xxxx01xxxx0xxxx0xxxx w 834 SVE orrs p_b_0 : p10_zer p_b_5 p_b_16
0010010100011000111001000000xxxx n 894 SVE pfalse p_b_0 :
00100101010110001100000xxxx0xxxx w 895 SVE pfirst p_b_0 : p5 p_b_0
001001010101000011xxxx0xxxx00000 w 786 SVE ptest : p10 p_b_5
00100101xx011000111000xxxxx0xxxx n 897 SVE ptrue p_size_bhsd_0 : pred_constr
00100101xx011001111000xxxxx0xxxx w 898 SVE ptrues p_size_bhsd_0 : pred_constr
00000101001100010100000xxxx0xxxx n 887 SVE punpkhi p_h_0 : p_b_5
00000101001100000100000xxxx0xxxx n 888 SVE punpklo p_h_0 : p_b_5
0010010100011001111100000000xxxx n 817 SVE rdffr p_b_0 :
Expand All @@ -196,6 +200,8 @@
00000100xx001100000xxxxxxxxxxxxx n 349 SVE sabd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00000100xx010100000xxxxxxxxxxxxx n 363 SVE sdiv z_size_sd_0 : p10_mrg_lo z_size_sd_0 z_size_sd_5
00000100xx010110000xxxxxxxxxxxxx n 794 SVE sdivr z_size_sd_0 : p10_mrg_lo z_size_sd_0 z_size_sd_5
001001010000xxxx01xxxx1xxxx1xxxx n 896 SVE sel p_b_0 : p10 p_b_5 p_b_16
00000101xx1xxxxx11xxxxxxxxxxxxxx n 896 SVE sel z_size_bhsd_0 : p10 z_size_bhsd_5 z_size_bhsd_16
00100101001011001001000000000000 n 819 SVE setffr :
00000100xx001000000xxxxxxxxxxxxx n 386 SVE smax z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00100101xx101000110xxxxxxxxxxxxx n 386 SVE smax z_size_bhsd_0 : z_size_bhsd_0 simm8_5
Expand Down Expand Up @@ -237,8 +243,8 @@
00000100xx1xxxxx000110xxxxxxxxxx n 425 SVE sqsub z0 : z5 z16 bhsd_sz
00100101xx10011011xxxxxxxxxxxxxx n 425 SVE sqsub z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1
00000100xx1xxxxx000110xxxxxxxxxx n 425 SVE sqsub z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16
1110010110xxxxxx000xxxxxxxx0xxxx n 457 SVE str svemem_gpr_simm9_vl : p0
1110010110xxxxxx010xxxxxxxxxxxxx n 457 SVE str svemem_gpr_simm9_vl : z0
1110010110xxxxxx000xxxxxxxx0xxxx n 457 SVE str svemem_gpr_simm9_vl : p0
1110010110xxxxxx010xxxxxxxxxxxxx n 457 SVE str svemem_gpr_simm9_vl : z0
00000100xx1xxxxx000001xxxxxxxxxx n 470 SVE sub z0 : z5 z16 bhsd_sz
00000100xx000001000xxxxxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00100101xx10000111xxxxxxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1
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116 changes: 116 additions & 0 deletions core/ir/aarch64/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8818,4 +8818,120 @@
#define INSTR_CREATE_eon_sve_imm(dc, Zdn, imm) \
instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm))

/**
* Creates a PFALSE instruction.
*
* This macro is used to encode the forms:
* \verbatim
* PFALSE <Pd>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
*/
#define INSTR_CREATE_pfalse_sve(dc, Pd) instr_create_1dst_0src(dc, OP_pfalse, Pd)

/**
* Creates a PFIRST instruction.
*
* This macro is used to encode the forms:
* \verbatim
* PFIRST <Pdn>.B, <Pg>, <Pdn>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pdn The source and destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
*/
#define INSTR_CREATE_pfirst_sve(dc, Pdn, Pg) \
instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn)

/**
* Creates a SEL instruction.
*
* This macro is used to encode the forms:
* \verbatim
* SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm)

/**
* Creates a SEL instruction.
*
* This macro is used to encode the forms:
* \verbatim
* SEL <Zd>.<Ts>, <Pv>, <Zn>.<Ts>, <Zm>.<Ts>
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Pv The first source predicate register, P (Predicate).
* \param Zn The second source vector register, Z (Scalable).
* \param Zm The third source vector register, Z (Scalable).
*/
#define INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm) \
instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm)

/**
* Creates an MOV instruction.
*
* This macro is used to encode the forms:
* \verbatim
* MOV <Pd>.B, <Pn>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
*/
#define INSTR_CREATE_mov_sve_pred(dc, Pd, Pn) \
instr_create_1dst_3src(dc, OP_orr, Pd, \
opnd_create_predicate_reg(opnd_get_reg(Pn), false), Pn, Pn)

/**
* Creates an MOVS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* MOVS <Pd>.B, <Pg>/Z, <Pn>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
*/
#define INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn) \
instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn)

/**
* Creates a PTRUE instruction.
*
* This macro is used to encode the forms:
* \verbatim
* PTRUE <Pd>.<Ts>{, <pattern>}
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param pattern The predicate constraint, see #dr_pred_constr_type_t.
*/
#define INSTR_CREATE_ptrue_sve(dc, Pd, pattern) \
instr_create_1dst_1src(dc, OP_ptrue, Pd, pattern)

/**
* Creates a PTRUES instruction.
*
* This macro is used to encode the forms:
* \verbatim
* PTRUES <Pd>.<Ts>{, <pattern>}
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param pattern The predicate constraint, see #dr_pred_constr_type_t.
*/
#define INSTR_CREATE_ptrues_sve(dc, Pd, pattern) \
instr_create_1dst_1src(dc, OP_ptrues, Pd, pattern)

#endif /* DR_IR_MACROS_AARCH64_H */
1 change: 1 addition & 0 deletions core/ir/aarch64/opnd_defs.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@
---------------------------xxxxx prfop # prefetch operation
------------------------xxx----- op2 # 3 bit immediate from 5-7
-----------------------xxxx----- p_b_5 # P register with a byte element size
-----------------------xxxx----- p5 # P register
-----------------------xxxx----- p5_zer # P register, zeroing
----------------------xxxxx----- w5 # W register (or WZR)
----------------------xxxxx----- x5 # X register (or XZR)
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