i#1312 AVX-512 support: Add general AVX-512 related enums and functio…

…ns. (#3497) Adds DR_REG_XMM16 - DR_REG_XMM31, DR_REG_YMM16 - DR_REG_YMM31 and their DR_REG_ZMM0 - DR_REG__ZMM31 siblings as well as DR_REG_K0 - DR_REG_K7. Adds 32 reserved enum numbers for each XMM, YMM and ZMM for potential future extensions. Deprecates reg_is_xmm(). Adds the functions reg_is_strictly_xmm(), reg_is_strictly_ymm(), reg_is_strictly_zmm() and reg_is_opmask(). Moves the OPSZ_ enum to start at 0, now overlapping the REG_ enum completely. There is no AVX-512 decoder/encoder yet, the enums are only partially tested e.g. through the size_name array and assertion in decode_shared.c and through the existing tests. Issue: #1312
DynamoRIO · Apr 11, 2019 · 053f6b6 · 053f6b6
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diff --git a/.travis.yml b/.travis.yml
@@ -145,7 +145,7 @@ before_deploy:
   # We should find a way to share (xref i#1565).
   # We support setting TAG_SUFFIX on triggered builds so we can have
   # multiple unique tags in one day (the patchlevel here is the day number).
-  - export GIT_TAG="cronbuild-7.1.$((`git log -n 1 --format=%ct` / (60*60*24)))${TAG_SUFFIX}"
+  - export GIT_TAG="cronbuild-7.90.$((`git log -n 1 --format=%ct` / (60*60*24)))${TAG_SUFFIX}"
   - git tag $GIT_TAG -a -m "Travis auto-generated tag for build $TRAVIS_BUILD_NUMBER."
 deploy:
   provider: releases

diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -484,7 +484,7 @@ endif (EXISTS "${PROJECT_SOURCE_DIR}/.svn")
 
 # N.B.: when updating this, update the git tag in .travis.yml.
 # We should find a way to share (xref i#1565).
-set(VERSION_NUMBER_DEFAULT "7.1.${VERSION_NUMBER_PATCHLEVEL}")
+set(VERSION_NUMBER_DEFAULT "7.90.${VERSION_NUMBER_PATCHLEVEL}")
 # do not store the default VERSION_NUMBER in the cache to prevent a stale one
 # from preventing future version updates in a pre-existing build dir
 set(VERSION_NUMBER "" CACHE STRING "Version number: leave empty for default")
@@ -1195,11 +1195,12 @@ math(EXPR VERSION_NUMBER_INTEGER
   "${VERSION_NUMBER_MAJOR}*100 + ${VERSION_NUMBER_MINOR}")
 
 # Every release since has had minor compat breakages.
+# 7.90 broke backcompat in DR_REG_ enums and OPSZ_ enums.
 # 6.0 broke backcompat in Linux injection, mod load event, etc.
 # 5.0 broke backcompat in drsyms and xmm opnd sizes
 # 4.1 broke backcompat in drsyms + 64-bit core (opcodes + reachability)
 # 4.0 broke backcompat in drmgr, drsyms, drinjectlib, and dr_get_milliseconds()
-set(OLDEST_COMPATIBLE_VERSION_DEFAULT "701")
+set(OLDEST_COMPATIBLE_VERSION_DEFAULT "790")
 set(OLDEST_COMPATIBLE_VERSION "" CACHE STRING
   "Oldest compatible version: leave empty for default")
 if ("${OLDEST_COMPATIBLE_VERSION}" STREQUAL "")

diff --git a/api/docs/release.dox b/api/docs/release.dox
@@ -133,6 +133,16 @@ Dr. Memory Framework (DRMF) in the same package as DynamoRIO.  DRMF
 provides the umbra, drsyscall, and drsymcache Extensions for use by
 clients.
 
+The changes between version \DR_VERSION and 7.1.0 include the following compatibility
+changes:
+
+ - Changes the enumeration of the DR_REG_ enum by adding x86 AVX-512 registers as well
+   as reserved ranges for future extensions.
+   This is a binary compatibility change for the DR_REG_ enum.
+ - Changes the enumeration of the OPSZ_ enum by moving its start back to 0. The OPSZ_
+   enum now completely overlaps the DR_REG_ enum.
+   This is a binary compatibility change for the OPSZ_ enum.
+
 The changes between version \DR_VERSION and 7.1.0 include the following minor
 compatibility changes:
 
@@ -145,6 +155,8 @@ compatibility changes:
    expression and code relying on this needs to be rewritten.
    DynamoRIO_NUM_SIMD_SLOTS_COMPATIBILITY is set automatically if clients target
    version 7.1.0 or earlier.
+ - Renamed mcontext's "ymm" structure to "simd".
+ - Deprecated reg_is_xmm() and reg_is_ymm().
 
 Further non-compatibility-affecting changes include:
 
@@ -158,6 +170,12 @@ Further non-compatibility-affecting changes include:
  - Added the define #MCXT_NUM_OPMASK_SLOTS for the number of AVX-512 OpMask registers.
  - Renamed mcontext's ymm structure into simd.
  - Added a new option -logprefix to drcov.
+ - Added the AVX-512 registers #DR_REG_XMM16 - #DR_REG_XMM31, #DR_REG_YMM16 -
+   #DR_REG_YMM31 and their #DR_REG_ZMM0 - #DR_REG_ZMM31 siblings as well as
+   #DR_REG_K0 - #DR_REG_K7.
+ - Added the function reg_is_opmask().
+ - Added the functions reg_is_strictly_xmm(), reg_is_strictly_ymm() and
+   reg_is_strictly_zmm().
 
 **************************************************
 <hr>

diff --git a/core/arch/aarch64/instr.c b/core/arch/aarch64/instr.c
@@ -335,19 +335,46 @@ reg_is_gpr(reg_id_t reg)
     return (DR_REG_X0 <= reg && reg <= DR_REG_WSP);
 }
 
+bool
+reg_is_opmask(reg_id_t reg)
+{
+    return false;
+}
+
+bool
+reg_is_strictly_zmm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_ymm(reg_id_t reg)
 {
+    /* i#1312: check why this assertion is here and not
+     * in the other x86 related reg_is_ functions.
+     */
     ASSERT_NOT_IMPLEMENTED(false); /* FIXME i#1569 */
     return false;
 }
 
+bool
+reg_is_strictly_ymm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_xmm(reg_id_t reg)
 {
     return false;
 }
 
+bool
+reg_is_strictly_xmm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_mmx(reg_id_t reg)
 {

diff --git a/core/arch/arm/instr.c b/core/arch/arm/instr.c
@@ -730,18 +730,42 @@ reg_is_simd(reg_id_t reg)
     return (reg >= DR_REG_Q0 && reg <= DR_REG_B31);
 }
 
+bool
+reg_is_opmask(reg_id_t reg)
+{
+    return false;
+}
+
+bool
+reg_is_strictly_zmm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_ymm(reg_id_t reg)
 {
     return false;
 }
 
+bool
+reg_is_strictly_ymm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_xmm(reg_id_t reg)
 {
     return false;
 }
 
+bool
+reg_is_strictly_xmm(reg_id_t reg)
+{
+    return false;
+}
+
 bool
 reg_is_mmx(reg_id_t reg)
 {

diff --git a/core/arch/asm_defines.asm b/core/arch/asm_defines.asm
@@ -100,6 +100,7 @@
 #  define MMWORD qword ptr
 #  define XMMWORD oword ptr
 #  define YMMWORD ymmword ptr
+#  define ZMMWORD zmmword ptr
 #  ifdef X64
 /* w/o the rip, gas won't use rip-rel and adds relocs that ld trips over */
 #   define SYMREF(sym) [rip + sym]
@@ -114,6 +115,7 @@
 #  define MMWORD /* nothing */
 #  define XMMWORD /* nothing */
 #  define YMMWORD /* nothing */
+#  define ZMMWORD /* nothing */
 /* XXX: this will NOT produce PIC code!  A multi-instr multi-local-data sequence
  * must be used.  See cleanup_and_terminate() for examples.
  */
@@ -178,6 +180,7 @@ ASSUME fs:_DATA @N@\
 # define MMWORD mmword ptr
 # define XMMWORD xmmword ptr
 # define YMMWORD ymmword ptr /* added in VS 2010 */
+# define ZMMWORD zmmword ptr /* XXX i#1312: supported by our supported version of VS? */
 /* ml64 uses rip-rel automatically */
 # define SYMREF(sym) [sym]
 # define HEX(n) 0##n##h
@@ -220,6 +223,7 @@ ASSUME fs:_DATA @N@\
 # define MMWORD qword
 # define XMMWORD oword
 # define YMMWORD yword
+# define ZMMWORD zword
 # ifdef X64
 #  define SYMREF(sym) [rel GLOBAL_REF(sym)]
 # else

diff --git a/core/arch/decode.h b/core/arch/decode.h
@@ -173,20 +173,15 @@ typedef struct _decode_info_t decode_info_t;
  * byte, so the largest value here needs to be <= 255.
  */
 enum {
-/* For x86, register enum values are used for TYPE_*REG but we only use them
- * as opnd_size_t when we have the type available, so we can overlap
- * the two enums by adding new registers consecutively to the reg enum.
- * The reg_id_t type is now wider, but for x86 we ensure our values
- * all fit via an assert in d_r_arch_init().
- * To maintain backward compatibility we keep the OPSZ_ constants
- * starting at the same spot, now midway through the reg enum:
- */
-#ifdef X86
-    OPSZ_NA = DR_REG_INVALID + 1,
-/**< Sentinel value: not a valid size. */ /* = 140 */
-#else
+    /* For x86, register enum values are used for TYPE_*REG but we only use them
+     * as opnd_size_t when we have the type available, so we can overlap
+     * the two enums. If needed, the function template_optype_is_reg can be used
+     * to check whether the operand type has an implicit size and stores the reg enum
+     * instead of the size enum.
+     * The reg_id_t type is now wider, but for x86 we ensure our values
+     * all fit via an assert in d_r_arch_init().
+     */
     OPSZ_NA = 0, /**< Sentinel value: not a valid size. */
-#endif
     OPSZ_FIRST = OPSZ_NA,
     OPSZ_0,   /**< 0 bytes, for "sizeless" operands (for Intel, code
                * 'm': used for both start addresses (lea, invlpg) and
@@ -302,7 +297,8 @@ enum {
     OPSZ_52,  /**< 52 bytes.  Needed for load/store of register lists. */
     OPSZ_56,  /**< 56 bytes.  Needed for load/store of register lists. */
     OPSZ_60,  /**< 60 bytes.  Needed for load/store of register lists. */
-    OPSZ_64,  /**< 64 bytes.  Needed for load/store of register lists. */
+    OPSZ_64,  /**< 64 bytes.  Needed for load/store of register lists.
+               * Also Intel: 64 bytes (512 bits) */
     OPSZ_68,  /**< 68 bytes.  Needed for load/store of register lists. */
     OPSZ_72,  /**< 72 bytes.  Needed for load/store of register lists. */
     OPSZ_76,  /**< 76 bytes.  Needed for load/store of register lists. */
@@ -389,10 +385,12 @@ enum {
     OPSZ_12_rex8_of_16,      /* 96 bits, or 64 with rex.w: 3/4 of XMM */
     OPSZ_14_of_16,           /* 112 bits; all but one word of XMM */
     OPSZ_15_of_16,           /* 120 bits: all but one byte of XMM */
-    OPSZ_8_of_16_vex32,      /* 64 bits, but can be half of XMM register; if
-                              * vex.L then is 256 bits (YMM or memory)
+    OPSZ_8_of_16_vex32,      /* 64 bits, but can be half of XMM register;
+                              * if vex.L then is 256 bits (YMM or memory);
+                              * if evex.L' then is 512 bits (ZMM or memory)
                               */
     OPSZ_16_of_32,           /* 128 bits: half of YMM */
+    /* XXX i#1312: Augment with new types specific to AVX-512. */
     OPSZ_SUBREG_START = OPSZ_1_of_4,
     OPSZ_SUBREG_END = OPSZ_16_of_32,
     OPSZ_LAST_ENUM, /* note last is NOT inclusive */

diff --git a/core/arch/decode_shared.c b/core/arch/decode_shared.c
@@ -62,148 +62,6 @@ decode_debug_checks_arch(void);
 #endif
 
 const char *const size_names[] = {
-#ifdef X86
-    "<invalid>" /* was <NULL> */,
-    "<invalid>" /* was rax */,
-    "<invalid>" /* was rcx */,
-    "<invalid>" /* was rdx */,
-    "<invalid>" /* was rbx */,
-    "<invalid>" /* was rsp */,
-    "<invalid>" /* was rbp */,
-    "<invalid>" /* was rsi */,
-    "<invalid>" /* was rdi */,
-    "<invalid>" /* was r8 */,
-    "<invalid>" /* was r9 */,
-    "<invalid>" /* was r10 */,
-    "<invalid>" /* was r11 */,
-    "<invalid>" /* was r12 */,
-    "<invalid>" /* was r13 */,
-    "<invalid>" /* was r14 */,
-    "<invalid>" /* was r15 */,
-    "<invalid>" /* was eax */,
-    "<invalid>" /* was ecx */,
-    "<invalid>" /* was edx */,
-    "<invalid>" /* was ebx */,
-    "<invalid>" /* was esp */,
-    "<invalid>" /* was ebp */,
-    "<invalid>" /* was esi */,
-    "<invalid>" /* was edi */,
-    "<invalid>" /* was r8d */,
-    "<invalid>" /* was r9d */,
-    "<invalid>" /* was r10d */,
-    "<invalid>" /* was r11d */,
-    "<invalid>" /* was r12d */,
-    "<invalid>" /* was r13d */,
-    "<invalid>" /* was r14d */,
-    "<invalid>" /* was r15d */,
-    "<invalid>" /* was ax */,
-    "<invalid>" /* was cx */,
-    "<invalid>" /* was dx */,
-    "<invalid>" /* was bx */,
-    "<invalid>" /* was sp */,
-    "<invalid>" /* was bp */,
-    "<invalid>" /* was si */,
-    "<invalid>" /* was di */,
-    "<invalid>" /* was r8w */,
-    "<invalid>" /* was r9w */,
-    "<invalid>" /* was r10w */,
-    "<invalid>" /* was r11w */,
-    "<invalid>" /* was r12w */,
-    "<invalid>" /* was r13w */,
-    "<invalid>" /* was r14w */,
-    "<invalid>" /* was r15w */,
-    "<invalid>" /* was al */,
-    "<invalid>" /* was cl */,
-    "<invalid>" /* was dl */,
-    "<invalid>" /* was bl */,
-    "<invalid>" /* was ah */,
-    "<invalid>" /* was ch */,
-    "<invalid>" /* was dh */,
-    "<invalid>" /* was bh */,
-    "<invalid>" /* was r8l */,
-    "<invalid>" /* was r9l */,
-    "<invalid>" /* was r10l */,
-    "<invalid>" /* was r11l */,
-    "<invalid>" /* was r12l */,
-    "<invalid>" /* was r13l */,
-    "<invalid>" /* was r14l */,
-    "<invalid>" /* was r15l */,
-    "<invalid>" /* was spl */,
-    "<invalid>" /* was bpl */,
-    "<invalid>" /* was sil */,
-    "<invalid>" /* was dil */,
-    "<invalid>" /* was mm0 */,
-    "<invalid>" /* was mm1 */,
-    "<invalid>" /* was mm2 */,
-    "<invalid>" /* was mm3 */,
-    "<invalid>" /* was mm4 */,
-    "<invalid>" /* was mm5 */,
-    "<invalid>" /* was mm6 */,
-    "<invalid>" /* was mm7 */,
-    "<invalid>" /* was xmm0 */,
-    "<invalid>" /* was xmm1 */,
-    "<invalid>" /* was xmm2 */,
-    "<invalid>" /* was xmm3 */,
-    "<invalid>" /* was xmm4 */,
-    "<invalid>" /* was xmm5 */,
-    "<invalid>" /* was xmm6 */,
-    "<invalid>" /* was xmm7 */,
-    "<invalid>" /* was xmm8 */,
-    "<invalid>" /* was xmm9 */,
-    "<invalid>" /* was xmm10 */,
-    "<invalid>" /* was xmm11 */,
-    "<invalid>" /* was xmm12 */,
-    "<invalid>" /* was xmm13 */,
-    "<invalid>" /* was xmm14 */,
-    "<invalid>" /* was xmm15 */,
-    "<invalid>" /* was st0 */,
-    "<invalid>" /* was st1 */,
-    "<invalid>" /* was st2 */,
-    "<invalid>" /* was st3 */,
-    "<invalid>" /* was st4 */,
-    "<invalid>" /* was st5 */,
-    "<invalid>" /* was st6 */,
-    "<invalid>" /* was st7 */,
-    "<invalid>" /* was es */,
-    "<invalid>" /* was cs */,
-    "<invalid>" /* was ss */,
-    "<invalid>" /* was ds */,
-    "<invalid>" /* was fs */,
-    "<invalid>" /* was gs */,
-    "<invalid>" /* was dr0 */,
-    "<invalid>" /* was dr1 */,
-    "<invalid>" /* was dr2 */,
-    "<invalid>" /* was dr3 */,
-    "<invalid>" /* was dr4 */,
-    "<invalid>" /* was dr5 */,
-    "<invalid>" /* was dr6 */,
-    "<invalid>" /* was dr7 */,
-    "<invalid>" /* was dr8 */,
-    "<invalid>" /* was dr9 */,
-    "<invalid>" /* was dr10 */,
-    "<invalid>" /* was dr11 */,
-    "<invalid>" /* was dr12 */,
-    "<invalid>" /* was dr13 */,
-    "<invalid>" /* was dr14 */,
-    "<invalid>" /* was dr15 */,
-    "<invalid>" /* was cr0 */,
-    "<invalid>" /* was cr1 */,
-    "<invalid>" /* was cr2 */,
-    "<invalid>" /* was cr3 */,
-    "<invalid>" /* was cr4 */,
-    "<invalid>" /* was cr5 */,
-    "<invalid>" /* was cr6 */,
-    "<invalid>" /* was cr7 */,
-    "<invalid>" /* was cr8 */,
-    "<invalid>" /* was cr9 */,
-    "<invalid>" /* was cr10 */,
-    "<invalid>" /* was cr11 */,
-    "<invalid>" /* was cr12 */,
-    "<invalid>" /* was cr13 */,
-    "<invalid>" /* was cr14 */,
-    "<invalid>" /* was cr15 */,
-    "<invalid>" /* was <invalid> */,
-#endif
     "OPSZ_NA",
     "OPSZ_lea",
     "OPSZ_1",