soc/power9/istep_9_7.c: XBus link training validation

Change-Id: Idbb17e19ec3f36e7f7e64e7d90a27f8ea9e0fe95
Signed-off-by: Sergii Dmytruk <[email protected]>

src/include/cpu/power/istep_9.h

@@ -8,5 +8,6 @@
 void istep_9_2(uint8_t chips);
 void istep_9_4(uint8_t chips);
 void istep_9_6(uint8_t chips);
+void istep_9_7(uint8_t chips);
 
 #endif /* CPU_PPC64_ISTEP8_H */

src/soc/ibm/power9/Makefile.inc

@@ -19,6 +19,7 @@ romstage-y += istep_8_11.c
 romstage-y += istep_9_2.c
 romstage-y += istep_9_4.c
 romstage-y += istep_9_6.c
+romstage-y += istep_9_7.c
 romstage-y += istep_10_10.c
 romstage-y += istep_10_12.c
 romstage-y += istep_10_13.c

src/soc/ibm/power9/istep_9_7.c

@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/power/istep_9.h>
+
+#include <console/console.h>
+#include <cpu/power/scom.h>
+#include <delay.h>
+#include <stdbool.h>
+
+#include "xbus.h"
+
+static void p9_fab_iovalid_link_validate(uint8_t chip)
+{
+	enum {
+		XBUS_LL1_IOEL_FIR_REG = 0x06011C00,
+		DL_FIR_LINK0_TRAINED_BIT = 0,
+		DL_FIR_LINK1_TRAINED_BIT = 1,
+	};
+
+	int i;
+
+	for (i = 0; i < 100; ++i) {
+		/* Only OBus seems to be retrained, so this XBus-only code is
+		 * much simpler compared to corresponding code in Hostboot */
+
+		uint64_t dl_fir_reg = get_scom(chip, XBUS_LL1_IOEL_FIR_REG);
+
+		bool dl_trained = (dl_fir_reg & PPC_BIT(DL_FIR_LINK0_TRAINED_BIT))
+			       && (dl_fir_reg & PPC_BIT(DL_FIR_LINK1_TRAINED_BIT));
+		if (dl_trained)
+			break;
+
+		udelay(1 * 1000); // 1ms
+	}
+
+	if (i == 100)
+		die("XBus link DL training failed\n");
+}
+
+static void p9_fab_iovalid(uint8_t chip)
+{
+	enum {
+		PERV_XB_CPLT_CONF1_OR = 0x06000019,
+		PERV_CPLT_CONF1_IOVALID_6D = 6,
+
+		PU_PB_CENT_SM0_PB_CENT_FIR_REG = 0x05011C00,
+		PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13 = 13,
+
+		PU_PB_CENT_SM1_EXTFIR_ACTION0_REG = 0x05011C34,
+		PU_PB_CENT_SM1_EXTFIR_ACTION1_REG = 0x05011C35,
+
+		PU_PB_CENT_SM1_EXTFIR_MASK_REG_AND = 0x05011C32,
+	};
+
+	uint64_t fbc_cent_fir_data;
+
+	/* Add delay for DD1.1+ procedure to compensate for lack of lane lock
+	 * polls */
+	udelay(100 * 1000); // 100ms
+
+	p9_fab_iovalid_link_validate(chip);
+
+	/* Clear RAS FIR mask for link if not already set up by SBE */
+	fbc_cent_fir_data = get_scom(chip, PU_PB_CENT_SM0_PB_CENT_FIR_REG);
+	if (!(fbc_cent_fir_data & PPC_BIT(PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13))) {
+		and_scom(chip, PU_PB_CENT_SM1_EXTFIR_ACTION0_REG,
+			 ~PPC_BIT(PERV_CPLT_CONF1_IOVALID_6D));
+		and_scom(chip, PU_PB_CENT_SM1_EXTFIR_ACTION1_REG,
+			 ~PPC_BIT(PERV_CPLT_CONF1_IOVALID_6D));
+		put_scom(chip, PU_PB_CENT_SM1_EXTFIR_MASK_REG_AND,
+			 ~PPC_BIT(PERV_CPLT_CONF1_IOVALID_6D));
+	}
+
+	/*
+	 * Use AND/OR mask registers to atomically update link specific fields
+	 * in iovalid control register.
+	 */
+	put_scom(chip, PERV_XB_CPLT_CONF1_OR,
+		 PPC_BIT(PERV_CPLT_CONF1_IOVALID_6D) |
+		 PPC_BIT(PERV_CPLT_CONF1_IOVALID_6D + 1));
+}
+
+void istep_9_7(uint8_t chips)
+{
+	printk(BIOS_EMERG, "starting istep 9.7\n");
+	report_istep(9,7);
+
+	if (chips != 0x01) {
+		p9_fab_iovalid(/*chip=*/0);
+		p9_fab_iovalid(/*chip=*/1);
+	}
+
+	printk(BIOS_EMERG, "ending istep 9.7\n");
+}

src/soc/ibm/power9/romstage.c

@@ -376,6 +376,7 @@ void main(void)
 	istep_9_2(chips);
 	istep_9_4(chips);
 	istep_9_6(chips);
+	istep_9_7(chips);
 
 	istep_10_10(&phb_active_mask, iovalid_enable);
 	istep_10_12();