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Always use SDK5 cache address if DSi mode is enabled
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ALSO: Revert from 32KB to 128KB
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@RocketRobz
RocketRobz committed Sep 16, 2018
1 parent 2cac4fc commit d4eaf18
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Showing 4 changed files with 45 additions and 42 deletions.
9 changes: 5 additions & 4 deletions bootloader/source/arm7/main.arm7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -407,9 +407,10 @@ static module_params_t* loadModuleParams(const tNDSHeader* ndsHeader, bool* foun
}

static bool isROMLoadableInRAM(const tNDSHeader* ndsHeader, const module_params_t* moduleParams, u32 consoleModel) {
return ((isSdk5(moduleParams) && consoleModel > 0 && getRomSizeNoArm9(ndsHeader) <= 0x01000000)
|| (!isSdk5(moduleParams) && consoleModel > 0 && getRomSizeNoArm9(ndsHeader) <= 0x017FC000)
|| (!isSdk5(moduleParams) && consoleModel == 0 && getRomSizeNoArm9(ndsHeader) <= 0x007FC000));
return ((dsiModeConfirmed && consoleModel > 0 && getRomSizeNoArm9(ndsHeader) <= 0x01000000)
|| (!dsiModeConfirmed && isSdk5(moduleParams) && consoleModel > 0 && getRomSizeNoArm9(ndsHeader) <= 0x01000000)
|| (!dsiModeConfirmed && !isSdk5(moduleParams) && consoleModel > 0 && getRomSizeNoArm9(ndsHeader) <= 0x017FC000)
|| (!dsiModeConfirmed && !isSdk5(moduleParams) && consoleModel == 0 && getRomSizeNoArm9(ndsHeader) <= 0x007FC000));
}

static vu32* storeArm9StartAddress(tNDSHeader* ndsHeader, const module_params_t* moduleParams) {
Expand Down Expand Up @@ -501,7 +502,7 @@ static void NTR_BIOS() {
}

static void loadROMintoRAM(const tNDSHeader* ndsHeader, const module_params_t* moduleParams, aFile file) {
char* romLocation = (char*)(isSdk5(moduleParams) ? ROM_SDK5_LOCATION : ROM_LOCATION);
char* romLocation = (char*)((dsiModeConfirmed || isSdk5(moduleParams)) ? ROM_SDK5_LOCATION : ROM_LOCATION);

// Load ROM into RAM
fileRead(romLocation, file, 0x4000 + ndsHeader->arm9binarySize, getRomSizeNoArm9(ndsHeader), 0);
Expand Down
4 changes: 2 additions & 2 deletions cardengine/arm7/source/cardengine.c
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ extern u32 saveCluster;
extern module_params_t* moduleParams;
extern u32 language;
extern u32 gottenSCFGExt;
extern u32 dsiMode; // SDK 5
extern u32 dsiMode;
extern u32 ROMinRAM;
extern u32 consoleModel;
extern u32 romread_LED;
Expand Down Expand Up @@ -124,7 +124,7 @@ static void initialize(void) {
#endif

ndsHeader = (tNDSHeader*)(isSdk5(moduleParams) ? NDS_HEADER_SDK5 : NDS_HEADER);
romLocation = (char*)(isSdk5(moduleParams) ? ROM_SDK5_LOCATION : ROM_LOCATION);
romLocation = (char*)((dsiMode || isSdk5(moduleParams)) ? ROM_SDK5_LOCATION : ROM_LOCATION);

initialized = true;
}
Expand Down
56 changes: 29 additions & 27 deletions cardengine/arm9/source/cardengine.c
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
#include <nds/arm9/exceptions.h>
#include <nds/arm9/cache.h>
#include <nds/system.h>
#include <nds/interrupts.h>
//#include <nds/interrupts.h>
#include <nds/ipc.h>
#include <nds/fifomessages.h>
#include <nds/memory.h> // tNDSHeader
Expand All @@ -47,7 +47,7 @@ extern vu32* volatile cardStruct0;

extern module_params_t* moduleParams;
extern u32 ROMinRAM;
extern u32 dsiMode; // SDK 5
extern u32 dsiMode;
extern u32 enableExceptionHandler;
extern u32 consoleModel;
extern u32 asyncPrefetch;
Expand All @@ -64,7 +64,7 @@ static u32 accessCounter = 0;

static tNDSHeader* ndsHeader = (tNDSHeader*)NDS_HEADER;
static u32 romLocation = ROM_LOCATION;
static u32 cacheAddress = CACHE_ADRESS_START; // SDK 5
static u32 cacheAddress = CACHE_ADRESS_START;
static u16 cacheSlots = retail_CACHE_SLOTS;

/*static u32 asyncReadSizeSubtract = 0;
Expand Down Expand Up @@ -106,8 +106,8 @@ static int getSlotForSector(u32 sector) {
}

static vu8* getCacheAddress(int slot) {
//return (vu32*)(cacheAddress + slot*_32KB_READ_SIZE);
return (vu8*)(cacheAddress + slot*_32KB_READ_SIZE);
//return (vu32*)(cacheAddress + slot*_128KB_READ_SIZE);
return (vu8*)(cacheAddress + slot*_128KB_READ_SIZE);
}

static void updateDescriptor(int slot, u32 sector) {
Expand Down Expand Up @@ -155,10 +155,10 @@ static void triggerAsyncPrefetch(u32 sector) {
if (ndsHeader->romSize > 0) {
if (sector > ndsHeader->romSize) {
sector = 0;
} else if ((sector+_32KB_READ_SIZE) > ndsHeader->romSize) {
for (u32 i = 0; i < _32KB_READ_SIZE; i++) {
} else if ((sector+_128KB_READ_SIZE) > ndsHeader->romSize) {
for (u32 i = 0; i < _128KB_READ_SIZE; i++) {
asyncReadSizeSubtract++;
if (((sector+_32KB_READ_SIZE)-asyncReadSizeSubtract) == ndsHeader->romSize) {
if (((sector+_128KB_READ_SIZE)-asyncReadSizeSubtract) == ndsHeader->romSize) {
break;
}
}
Expand All @@ -176,7 +176,7 @@ static void triggerAsyncPrefetch(u32 sector) {
vu8* buffer = getCacheAddress(slot);
if (needFlushDCCache) {
DC_FlushRange((u8*)buffer, _32KB_READ_SIZE);
DC_FlushRange((u8*)buffer, _128KB_READ_SIZE);
}
cacheDescriptor[slot] = sector;
Expand All @@ -185,7 +185,7 @@ static void triggerAsyncPrefetch(u32 sector) {
// write the command
sharedAddr[0] = (vu32)buffer;
sharedAddr[1] = _32KB_READ_SIZE-asyncReadSizeSubtract;
sharedAddr[1] = _128KB_READ_SIZE-asyncReadSizeSubtract;
sharedAddr[2] = sector;
sharedAddr[3] = commandRead;
Expand Down Expand Up @@ -242,7 +242,7 @@ static inline bool isHGSS(const tNDSHeader* ndsHeader) {

static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8* dst, u32 src, u32 len, u32 page, u8* cacheBuffer, u32* cachePage) {
u32 commandRead;
u32 sector = (src/_32KB_READ_SIZE)*_32KB_READ_SIZE;
u32 sector = (src/_128KB_READ_SIZE)*_128KB_READ_SIZE;

accessCounter++;

Expand All @@ -252,7 +252,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
processAsyncCommand();
}*/

if (page == src && len > _32KB_READ_SIZE && (u32)dst < 0x02700000 && (u32)dst > 0x02000000 && (u32)dst % 4 == 0) {
if (page == src && len > _128KB_READ_SIZE && (u32)dst < 0x02700000 && (u32)dst > 0x02000000 && (u32)dst % 4 == 0) {
/*if (asyncPrefetch && pAC) {
getAsyncSector();
}*/
Expand All @@ -262,7 +262,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8

//cacheFlush();

REG_IME = 0;
//REG_IME = 0;

sharedAddr[0] = (vu32)dst;
sharedAddr[1] = len;
Expand All @@ -273,14 +273,14 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8

waitForArm7();

REG_IME = 1;
//REG_IME = 1;

} else {
// Read via the main RAM cache
while(len > 0) {
int slot = getSlotForSector(sector);
vu8* buffer = getCacheAddress(slot);
//u32 nextSector = sector+_32KB_READ_SIZE;
//u32 nextSector = sector+_128KB_READ_SIZE;
// Read max CACHE_READ_SIZE via the main RAM cache
if (slot == -1) {
/*if (asyncPrefetch && pAC) {
Expand All @@ -295,22 +295,22 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
buffer = getCacheAddress(slot);

if (needFlushDCCache) {
DC_FlushRange((u8*)buffer, _32KB_READ_SIZE);
DC_FlushRange((u8*)buffer, _128KB_READ_SIZE);
}

REG_IME = 0;
//REG_IME = 0;

// Write the command
sharedAddr[0] = (vu32)buffer;
sharedAddr[1] = _32KB_READ_SIZE;
sharedAddr[1] = _128KB_READ_SIZE;
sharedAddr[2] = sector;
sharedAddr[3] = commandRead;

IPC_SendSync(0xEE24);

waitForArm7();

REG_IME = 1;
//REG_IME = 1;
}
updateDescriptor(slot, sector);

Expand Down Expand Up @@ -338,8 +338,8 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
}*/

u32 len2 = len;
if ((src - sector) + len2 > _32KB_READ_SIZE) {
len2 = sector - src + _32KB_READ_SIZE;
if ((src - sector) + len2 > _128KB_READ_SIZE) {
len2 = sector - src + _128KB_READ_SIZE;
}

if (len2 > 512) {
Expand Down Expand Up @@ -403,7 +403,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
src = cardStruct[0];
dst = (u8*)cardStruct[1];
page = (src / 512) * 512;
sector = (src / _32KB_READ_SIZE) * _32KB_READ_SIZE;
sector = (src / _128KB_READ_SIZE) * _128KB_READ_SIZE;
accessCounter++;
}
}
Expand All @@ -429,7 +429,7 @@ static inline int cardReadRAM(vu32* volatile cardStruct, u32* cacheStruct, u8* d

sharedAddr[0] = dst;
sharedAddr[1] = len;
sharedAddr[2] = ((isSdk5(moduleParams) ? dev_CACHE_ADRESS_START_SDK5 : romLocation)-0x4000-ndsHeader->arm9binarySize)+src;
sharedAddr[2] = ((dsiMode || isSdk5(moduleParams)) ? dev_CACHE_ADRESS_START_SDK5 : romLocation)-0x4000-ndsHeader->arm9binarySize)+src;
sharedAddr[3] = commandRead;

IPC_SendSync(0xEE24);
Expand All @@ -439,7 +439,7 @@ static inline int cardReadRAM(vu32* volatile cardStruct, u32* cacheStruct, u8* d
#endif

// Copy directly
memcpy(dst, (u8*)(((isSdk5(moduleParams) ? dev_CACHE_ADRESS_START_SDK5 : romLocation)-0x4000-ndsHeader->arm9binarySize)+src),len);
memcpy(dst, (u8*)((((dsiMode || isSdk5(moduleParams)) ? dev_CACHE_ADRESS_START_SDK5 : romLocation)-0x4000-ndsHeader->arm9binarySize)+src),len);

// Update cardi common
cardStruct[0] = src + len;
Expand All @@ -453,7 +453,7 @@ static inline int cardReadRAM(vu32* volatile cardStruct, u32* cacheStruct, u8* d

sharedAddr[0] = page;
sharedAddr[1] = len2;
sharedAddr[2] = (romLocation-0x4000-ndsHeader->arm9binarySize)+page;
sharedAddr[2] = (((dsiMode || isSdk5(moduleParams)) ? dev_CACHE_ADRESS_START_SDK5 : romLocation)-0x4000-ndsHeader->arm9binarySize)+page;
sharedAddr[3] = commandRead;

IPC_SendSync(0xEE24);
Expand All @@ -463,7 +463,7 @@ static inline int cardReadRAM(vu32* volatile cardStruct, u32* cacheStruct, u8* d
#endif

// Read via the 512b ram cache
memcpy(cacheBuffer, (u8*)((romLocation - 0x4000 - ndsHeader->arm9binarySize) + page), 512);
memcpy(cacheBuffer, (u8*)((((dsiMode || isSdk5(moduleParams)) ? dev_CACHE_ADRESS_START_SDK5 : romLocation) - 0x4000 - ndsHeader->arm9binarySize) + page), 512);
*cachePage = page;
(*readCachedRef)(cacheStruct);
}
Expand All @@ -483,6 +483,8 @@ int cardRead(u32* cacheStruct, u8* dst0, u32 src0, u32 len0) {
if (!flagsSet) {
if (isSdk5(moduleParams)) {
ndsHeader = (tNDSHeader*)NDS_HEADER_SDK5;
}
if (dsiMode || isSdk5(moduleParams)) {
romLocation = ROM_SDK5_LOCATION;
cacheAddress = retail_CACHE_ADRESS_START_SDK5;
cacheSlots = retail_CACHE_SLOTS_SDK5;
Expand All @@ -492,7 +494,7 @@ int cardRead(u32* cacheStruct, u8* dst0, u32 src0, u32 len0) {
cacheSlots = HGSS_CACHE_SLOTS; // Use smaller cache size to avoid timing issues
hgssFix = true;
} else if (consoleModel > 0) {
if (isSdk5(moduleParams)) {
if (dsiMode || isSdk5(moduleParams)) {
// SDK 5
cacheAddress = dev_CACHE_ADRESS_START_SDK5;
}
Expand Down
18 changes: 9 additions & 9 deletions common/include/locations.h
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Original file line number Diff line number Diff line change
Expand Up @@ -30,25 +30,25 @@
#define ROM_LOCATION 0x0C804000
#define ROM_SDK5_LOCATION 0x0D000000

#define CACHE_ADRESS_START 0x0C808000
#define CACHE_ADRESS_START 0x0C920000
#define retail_CACHE_ADRESS_START_SDK5 0x0C480000

//#define retail_CACHE_ADRESS_SIZE 0x7F8000
//#define retail_CACHE_ADRESS_SIZE 0x6E0000
//#define retail_CACHE_ADRESS_SIZE_SDK5 0x280000

#define retail_CACHE_SLOTS 0xFF
#define retail_CACHE_SLOTS_SDK5 0x50
#define retail_CACHE_SLOTS 0x37
#define retail_CACHE_SLOTS_SDK5 0x14

#define dev_CACHE_ADRESS_START_SDK5 0x0D000000

//#define dev_CACHE_ADRESS_SIZE 0x17F8000
//#define dev_CACHE_ADRESS_SIZE 0x16E0000
//#define dev_CACHE_ADRESS_SIZE_SDK5 0x1000000

#define dev_CACHE_SLOTS 0x2FF
#define dev_CACHE_SLOTS_SDK5 0x200
#define dev_CACHE_SLOTS 0xB7
#define dev_CACHE_SLOTS_SDK5 0x80

//#define HGSS_CACHE_ADRESS_SIZE 0x1F8000
//#define HGSS_CACHE_ADRESS_SIZE 0x1E0000

#define HGSS_CACHE_SLOTS 0x3F
#define HGSS_CACHE_SLOTS 0xF

#endif // LOCATIONS_H

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