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Try 48KB cache chunk size
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@RocketRobz
RocketRobz committed Sep 3, 2018
1 parent 7fc23fa commit 0c3251c
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Showing 2 changed files with 25 additions and 24 deletions.
31 changes: 16 additions & 15 deletions cardengine/arm9/source/cardengine.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
#include "cardengine.h"
#include "locations.h"

#define _48KB_READ_SIZE 0xC000
#define _32KB_READ_SIZE 0x8000
#define _64KB_READ_SIZE 0x10000
#define _128KB_READ_SIZE 0x20000
Expand Down Expand Up @@ -105,8 +106,8 @@ static int getSlotForSector(u32 sector) {
}

static vu8* getCacheAddress(int slot) {
//return (vu32*)(cacheAddress + slot*_64KB_READ_SIZE);
return (vu8*)(cacheAddress + slot*_64KB_READ_SIZE);
//return (vu32*)(cacheAddress + slot*_48KB_READ_SIZE);
return (vu8*)(cacheAddress + slot*_48KB_READ_SIZE);
}

static void updateDescriptor(int slot, u32 sector) {
Expand Down Expand Up @@ -154,10 +155,10 @@ static void triggerAsyncPrefetch(u32 sector) {
if (ndsHeader->romSize > 0) {
if (sector > ndsHeader->romSize) {
sector = 0;
} else if ((sector+_64KB_READ_SIZE) > ndsHeader->romSize) {
for (u32 i = 0; i < _64KB_READ_SIZE; i++) {
} else if ((sector+_48KB_READ_SIZE) > ndsHeader->romSize) {
for (u32 i = 0; i < _48KB_READ_SIZE; i++) {
asyncReadSizeSubtract++;
if (((sector+_64KB_READ_SIZE)-asyncReadSizeSubtract) == ndsHeader->romSize) {
if (((sector+_48KB_READ_SIZE)-asyncReadSizeSubtract) == ndsHeader->romSize) {
break;
}
}
Expand All @@ -175,7 +176,7 @@ static void triggerAsyncPrefetch(u32 sector) {
vu8* buffer = getCacheAddress(slot);
if (needFlushDCCache) {
DC_FlushRange((u8*)buffer, _64KB_READ_SIZE);
DC_FlushRange((u8*)buffer, _48KB_READ_SIZE);
}
cacheDescriptor[slot] = sector;
Expand All @@ -184,7 +185,7 @@ static void triggerAsyncPrefetch(u32 sector) {
// write the command
sharedAddr[0] = (vu32)buffer;
sharedAddr[1] = _64KB_READ_SIZE-asyncReadSizeSubtract;
sharedAddr[1] = _48KB_READ_SIZE-asyncReadSizeSubtract;
sharedAddr[2] = sector;
sharedAddr[3] = commandRead;
Expand Down Expand Up @@ -241,7 +242,7 @@ static inline bool isHGSS(const tNDSHeader* ndsHeader) {

static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8* dst, u32 src, u32 len, u32 page, u8* cacheBuffer, u32* cachePage) {
u32 commandRead;
u32 sector = (src/_64KB_READ_SIZE)*_64KB_READ_SIZE;
u32 sector = (src/_48KB_READ_SIZE)*_48KB_READ_SIZE;

accessCounter++;

Expand All @@ -251,7 +252,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
processAsyncCommand();
}*/

if (page == src && len > _64KB_READ_SIZE && (u32)dst < 0x02700000 && (u32)dst > 0x02000000 && (u32)dst % 4 == 0) {
if (page == src && len > _48KB_READ_SIZE && (u32)dst < 0x02700000 && (u32)dst > 0x02000000 && (u32)dst % 4 == 0) {
/*if (asyncPrefetch && pAC) {
getAsyncSector();
}*/
Expand All @@ -275,7 +276,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
while(len > 0) {
int slot = getSlotForSector(sector);
vu8* buffer = getCacheAddress(slot);
//u32 nextSector = sector+_64KB_READ_SIZE;
//u32 nextSector = sector+_48KB_READ_SIZE;
// Read max CACHE_READ_SIZE via the main RAM cache
if (slot == -1) {
/*if (asyncPrefetch && pAC) {
Expand All @@ -290,14 +291,14 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
buffer = getCacheAddress(slot);

if (needFlushDCCache) {
DC_FlushRange((u8*)buffer, _64KB_READ_SIZE);
DC_FlushRange((u8*)buffer, _48KB_READ_SIZE);
}

//REG_IME = 0;

// Write the command
sharedAddr[0] = (vu32)buffer;
sharedAddr[1] = _64KB_READ_SIZE;
sharedAddr[1] = _48KB_READ_SIZE;
sharedAddr[2] = sector;
sharedAddr[3] = commandRead;

Expand Down Expand Up @@ -333,8 +334,8 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
}

u32 len2 = len;
if ((src - sector) + len2 > _64KB_READ_SIZE) {
len2 = sector - src + _64KB_READ_SIZE;
if ((src - sector) + len2 > _48KB_READ_SIZE) {
len2 = sector - src + _48KB_READ_SIZE;
}

if (len2 > 512) {
Expand Down Expand Up @@ -398,7 +399,7 @@ static inline int cardReadNormal(vu32* volatile cardStruct, u32* cacheStruct, u8
src = cardStruct[0];
dst = (u8*)cardStruct[1];
page = (src / 512) * 512;
sector = (src / _64KB_READ_SIZE) * _64KB_READ_SIZE;
sector = (src / _48KB_READ_SIZE) * _48KB_READ_SIZE;
accessCounter++;
}
}
Expand Down
18 changes: 9 additions & 9 deletions common/include/locations.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,25 +30,25 @@
#define ROM_LOCATION 0x0C804000
#define ROM_SDK5_LOCATION 0x0D000000

#define CACHE_ADRESS_START 0x0C810000
#define CACHE_ADRESS_START 0x0C804000
#define retail_CACHE_ADRESS_START_SDK5 0x0C480000

//#define retail_CACHE_ADRESS_SIZE 0x7F0000
//#define retail_CACHE_ADRESS_SIZE 0x7FC000
//#define retail_CACHE_ADRESS_SIZE_SDK5 0x280000

#define retail_CACHE_SLOTS 0x7F
#define retail_CACHE_SLOTS_SDK5 0x28
#define retail_CACHE_SLOTS 0xAA
#define retail_CACHE_SLOTS_SDK5 0x35

#define dev_CACHE_ADRESS_START_SDK5 0x0D000000

//#define dev_CACHE_ADRESS_SIZE 0x17F0000
//#define dev_CACHE_ADRESS_SIZE 0x17FC000
//#define dev_CACHE_ADRESS_SIZE_SDK5 0x1000000

#define dev_CACHE_SLOTS 0x17F
#define dev_CACHE_SLOTS_SDK5 0x100
#define dev_CACHE_SLOTS 0x1FF
#define dev_CACHE_SLOTS_SDK5 0x155

//#define HGSS_CACHE_ADRESS_SIZE 0x1F0000
//#define HGSS_CACHE_ADRESS_SIZE 0x1FC000

#define HGSS_CACHE_SLOTS 0x1F
#define HGSS_CACHE_SLOTS 0x2A

#endif // LOCATIONS_H

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