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Given the actual qubit topology (probably as a graph-like structure) we may restrict the E-VQE random selection to those gates which are actually implementable via the hardware. This way we can make sure that the generated circuits map directly to physical implementations on the hardware.
The text was updated successfully, but these errors were encountered:
Given the actual qubit topology (probably as a graph-like structure) we may restrict the E-VQE random selection to those gates which are actually implementable via the hardware. This way we can make sure that the generated circuits map directly to physical implementations on the hardware.
The text was updated successfully, but these errors were encountered: