[RISC-V] ECLIC Port and GD32VF103 HAL Support #266
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Could you rebase your branch? |
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Rebased and pushed, don't know how this happened in the first place. |
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Rebased and ready to merge. I updated the first comment as well :-). |
KarlK90
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fpoussin
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Thank you! |
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This pull request adds ChibiOS support for the RISC-V ECLIC architecture by Nucleisys as well as a HAL Port for the GD32VF103 MCU family which is based on this architecture.
The GD32VF103 has been developed by GigaDevice and is a largely API compatible STM32F103/F105/F107 "clone" with a RISC-V RV32IMAC core.
(Some) Differences:
Clock tree is mix of STM32F103 and STM32F105/STM32F107
USB OTG instead of USB Device peripheral
I2C supports Fast Mode Plus
SPI supports TI mode and NSS pulse mode
USB Clock prescalers with values 2 and 2.5 that allow a core Sysclock of 96MHz and 120MHz (Out of spec but works fine)
USB-DFU Bootloader!
My approach was to copy the existing Chibios STM32F103 HAL drivers and rename every register to the correct GigaDevice definition. (I talked to Giovanni about this and this was the preferred approach https://forum.chibios.org/viewtopic.php?f=8&t=5758)
So far I have tested:
GPIO
PWM
UART
DMA
USB OTG
I2C
So far untested:
SPI
RTC
ADC
FLASH
GPT
ICU
CAN
WGD
DAC
The I2C peripheral driver has a timing bug and randomly locks-up that I will address in a different pull request, all other tested drivers work flawless (at least for me).
I also added board definitions for the sipeed longan nano board as well as a usb cdc demo ported from STM.
Please let me know If this is good to merge. :-)