Added the implementation of embedded flash for WB32 MCU.

ChibiOS · Jul 7, 2022 · 5279504 · 5279504
1 parent 022d0ec
commit 5279504
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Showing 10 changed files with 1,333 additions and 5 deletions.
diff --git a/os/common/ext/CMSIS/WB32/WB32F3G71xx/wb32f3g71xx.h b/os/common/ext/CMSIS/WB32/WB32F3G71xx/wb32f3g71xx.h
@@ -945,8 +945,24 @@ typedef struct
   #warning Not supported compiler type
 #endif
 
-
-
+static const uint32_t flash_size_code_map[16] = {
+  0x80000,    /* 512kB */
+  0x8000,     /* 32kB */
+  0x60000,    /* 384kB */
+  0x40000,    /* 256kB */
+  0x20000,    /* 128kB */
+  0x8000,     /* 32kB */
+  0x18000,    /* 96kB */
+  0x10000,    /* 64kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x30000,    /* 192kB */
+};
 
 /* ================================================================================ */
 /* ================              Peripheral memory map             ================ */
@@ -958,6 +974,9 @@ typedef struct
 #define SRAM_BB_BASE              ((uint32_t)0x22000000UL)          /*!< SRAM base address in the bit-band region */
 #define PERIPH_BB_BASE            ((uint32_t)0x42000000UL)          /*!< Peripheral base address in the bit-band region */
 
+#define SYS_MEMSE                 ((uint32_t)0x40016404UL)
+#define FLASH_SIZE                flash_size_code_map[(*((volatile uint32_t *)(SYS_MEMSE))) & 0xFU]
+
 #define APB1PERIPH_BASE       PERIPH_BASE
 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x08000)
 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x10000)

diff --git a/os/common/ext/CMSIS/WB32/WB32FQ95xx/wb32fq95xx.h b/os/common/ext/CMSIS/WB32/WB32FQ95xx/wb32fq95xx.h
@@ -890,6 +890,24 @@ typedef struct
   #warning Not supported compiler type
 #endif
 
+static const uint32_t flash_size_code_map[16] = {
+  0x80000,    /* 512kB */
+  0x8000,     /* 32kB */
+  0x60000,    /* 384kB */
+  0x40000,    /* 256kB */
+  0x20000,    /* 128kB */
+  0x8000,     /* 32kB */
+  0x18000,    /* 96kB */
+  0x10000,    /* 64kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x8000,     /* 32kB */
+  0x30000,    /* 192kB */
+};
 
 /* ================================================================================ */
 /* ================              Peripheral memory map             ================ */
@@ -901,6 +919,9 @@ typedef struct
 #define SRAM_BB_BASE              ((uint32_t)0x22000000UL)          /*!< SRAM base address in the bit-band region */
 #define PERIPH_BB_BASE            ((uint32_t)0x42000000UL)          /*!< Peripheral base address in the bit-band region */
 
+#define SYS_MEMSE                 ((uint32_t)0x40016404UL)
+#define FLASH_SIZE                flash_size_code_map[(*((volatile uint32_t *)(SYS_MEMSE))) & 0xFU]
+
 #define APB1PERIPH_BASE       PERIPH_BASE
 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x08000)
 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x10000)