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Fix the issue when the CH_CFG_ST_TIMEDELTA configuration is set to 2.
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wb committed Jul 25, 2024
1 parent 5621625 commit 3aa9e4d
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Showing 7 changed files with 27 additions and 21 deletions.
4 changes: 2 additions & 2 deletions demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h
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Expand Up @@ -63,7 +63,7 @@
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#define CH_CFG_ST_RESOLUTION 16
#endif

/**
Expand Down Expand Up @@ -100,7 +100,7 @@
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 0
#define CH_CFG_ST_TIMEDELTA 2
#endif

/** @} */
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6 changes: 3 additions & 3 deletions demos/WB32/RT-WB32F3G71-RTC/main.c
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Expand Up @@ -121,9 +121,9 @@ int main(void) {
while (true){
chThdSleepSeconds(2);
rtcGetTime(&RTCD1, &timespec);
chprintf((BaseSequentialStream *)&SERIAL_DEBUG_DRIVER,
"lsi sleep %ds year = %d month = %d dstflag=%d dayofweek = %d day = %d millisecond = %d\r\n",
RTC_ALARMPERIOD, timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond);
// chprintf((BaseSequentialStream *)&SERIAL_DEBUG_DRIVER,
// "lsi sleep %ds year = %d month = %d dstflag=%d dayofweek = %d day = %d millisecond = %d\r\n",
// RTC_ALARMPERIOD, timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond);
chThdSleepSeconds(3);

chSysDisable();
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4 changes: 2 additions & 2 deletions demos/WB32/RT-WB32FQ95-GENERIC/cfg/chconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#define CH_CFG_ST_RESOLUTION 16
#endif

/**
Expand Down Expand Up @@ -100,7 +100,7 @@
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 0
#define CH_CFG_ST_TIMEDELTA 2
#endif

/** @} */
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10 changes: 5 additions & 5 deletions os/hal/ports/WB32/LLD/TIMv1/hal_st_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -243,22 +243,22 @@ void st_lld_serve_interrupt(void) {
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if ST_LLD_NUM_ALARMS > 1
if ((sr & TIM_SR_CC2IF) != 0U) {
if (st_callbacks[2] != NULL) {
st_callbacks[0](1U);
if (st_callbacks[1] != NULL) {
st_callbacks[1](1U);
}
}
#endif
#if ST_LLD_NUM_ALARMS > 2
if ((sr & TIM_SR_CC3IF) != 0U) {
if (st_callbacks[2] != NULL) {
st_callbacks[1](2U);
st_callbacks[2](2U);
}
}
#endif
#if ST_LLD_NUM_ALARMS > 3
if ((sr & TIM_SR_CC4IF) != 0U) {
if (st_callbacks[2] != NULL) {
st_callbacks[2](3U);
if (st_callbacks[3] != NULL) {
st_callbacks[3](3U);
}
}
#endif
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8 changes: 7 additions & 1 deletion os/hal/ports/WB32/LLD/TIMv1/hal_st_lld.h
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Expand Up @@ -154,7 +154,7 @@
#define ST_LLD_NUM_ALARMS WB32_ST_ENFORCE_ALARMS
#endif

#elif OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#elif OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

#define WB32_ST_USE_SYSTICK TRUE
#define WB32_ST_USE_TIM2 FALSE
Expand Down Expand Up @@ -225,8 +225,10 @@ static inline void st_lld_start_alarm(systime_t abstime) {
WB32_ST_TIM->SR = 0;
#if ST_LLD_NUM_ALARMS == 1
WB32_ST_TIM->DIER = WB32_TIM_DIER_CC1IE;
WB32_ST_TIM->CCER = WB32_TIM_CCER_CC1E;
#else
WB32_ST_TIM->DIER |= WB32_TIM_DIER_CC1IE;
WB32_ST_TIM->CCER |= WB32_TIM_CCER_CC1E;
#endif
}

Expand All @@ -239,8 +241,10 @@ static inline void st_lld_stop_alarm(void) {

#if ST_LLD_NUM_ALARMS == 1
WB32_ST_TIM->DIER = 0U;
WB32_ST_TIM->CCER = 0U;
#else
WB32_ST_TIM->DIER &= ~WB32_TIM_DIER_CC1IE;
WB32_ST_TIM->CCER &= ~WB32_TIM_CCER_CC1E;
#endif
}

Expand Down Expand Up @@ -300,6 +304,7 @@ static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
WB32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
WB32_ST_TIM->SR = 0;
WB32_ST_TIM->DIER |= (WB32_TIM_DIER_CC1IE << alarm);
WB32_ST_TIM->CCER |= (WB32_TIM_CCER_CC1E << (alarm * 4));
}

/**
Expand All @@ -314,6 +319,7 @@ static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
static inline void st_lld_stop_alarm_n(unsigned alarm) {

WB32_ST_TIM->DIER &= ~(WB32_TIM_DIER_CC1IE << alarm);
WB32_ST_TIM->CCER &= ~(WB32_TIM_CCER_CC1E << (alarm * 4));
}

/**
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8 changes: 4 additions & 4 deletions os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h
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Expand Up @@ -99,13 +99,13 @@
#define WB32_HAS_TIM3 TRUE
#define WB32_HAS_TIM4 TRUE

#define WB32_TIM1_IS_32BITS TRUE
#define WB32_TIM1_IS_32BITS FALSE
#define WB32_TIM1_CHANNELS 4
#define WB32_TIM2_IS_32BITS TRUE
#define WB32_TIM2_IS_32BITS FALSE
#define WB32_TIM2_CHANNELS 4
#define WB32_TIM3_IS_32BITS TRUE
#define WB32_TIM3_IS_32BITS FALSE
#define WB32_TIM3_CHANNELS 4
#define WB32_TIM4_IS_32BITS TRUE
#define WB32_TIM4_IS_32BITS FALSE
#define WB32_TIM4_CHANNELS 4

/* I2C attributes */
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8 changes: 4 additions & 4 deletions os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h
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Original file line number Diff line number Diff line change
Expand Up @@ -99,13 +99,13 @@
#define WB32_HAS_TIM3 TRUE
#define WB32_HAS_TIM4 TRUE

#define WB32_TIM1_IS_32BITS TRUE
#define WB32_TIM1_IS_32BITS FALSE
#define WB32_TIM1_CHANNELS 4
#define WB32_TIM2_IS_32BITS TRUE
#define WB32_TIM2_IS_32BITS FALSE
#define WB32_TIM2_CHANNELS 4
#define WB32_TIM3_IS_32BITS TRUE
#define WB32_TIM3_IS_32BITS FALSE
#define WB32_TIM3_CHANNELS 4
#define WB32_TIM4_IS_32BITS TRUE
#define WB32_TIM4_IS_32BITS FALSE
#define WB32_TIM4_CHANNELS 4

/* I2C attributes */
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