Processer Design

This is the first term project developed for CSE3015 Digital Logic Design Course in Fall 2019.

Members of project team are listed below:

• Havva Karaçam ✨
• Ömer Faruk Çakı
• Cem Güleç 🚀

First iteration: Assembler design
Second iteration: Logisim design
Third iteration: Verilog design