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Merge pull request #412 from cuihantao/develop
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New minor release
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cuihantao authored Feb 13, 2023
2 parents fa514b9 + 87eac2f commit 7961a50
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Showing 3 changed files with 22 additions and 10 deletions.
10 changes: 5 additions & 5 deletions andes/models/pss/ieeest.py
Original file line number Diff line number Diff line change
Expand Up @@ -69,11 +69,11 @@ def __init__(self, system, config):
info='Input signal',
)

self.sig.v_str = 'SW_s1*(omega-1) + SW_s2*0 + SW_s3*(tm0/SnSb) + ' \
'SW_s4*(tm-tm0) + SW_s5*v + SW_s6*0'
self.sig.v_str = 'ue * ( SW_s1*(omega-1) + SW_s2*0 + SW_s3*(tm0/SnSb) + ' \
'SW_s4*(tm-tm0) + SW_s5*v + SW_s6*0 )'

self.sig.e_str = 'SW_s1*(omega-1) + SW_s2*(f-1) + SW_s3*(te/SnSb) + ' \
'SW_s4*(tm-tm0) + SW_s5*v + SW_s6*dv_v - sig'
self.sig.e_str = 'ue * ( SW_s1*(omega-1) + SW_s2*(f-1) + SW_s3*(te/SnSb) + ' \
'SW_s4*(tm-tm0) + SW_s5*v + SW_s6*dv_v ) - sig'

self.F1 = Lag2ndOrd(u=self.sig, K=1, T1=self.A1, T2=self.A2)

Expand All @@ -94,7 +94,7 @@ def __init__(self, system, config):

self.OLIM = Limiter(u=self.v, lower=self.VCLr, upper=self.VCUr, info='output limiter')

self.vsout.e_str = 'OLIM_zi * Vss - vsout'
self.vsout.e_str = 'ue * OLIM_zi * Vss - vsout'


class IEEEST(IEEESTData, IEEESTModel):
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16 changes: 14 additions & 2 deletions andes/models/pss/pssbase.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
import numpy as np

from andes.core import (ModelData, IdxParam, Model, ExtParam,
ExtState, ExtService, ExtAlgeb, Algeb)
ExtState, ExtService, ExtAlgeb, Algeb, ConstService)
from andes.core.service import Replace, DataSelect, DeviceFinder

logger = logging.getLogger(__name__)
Expand All @@ -29,6 +29,18 @@ def __init__(self, system, config):
self.group = 'PSS'
self.flags.update({'tds': True})

# from synchronous exciters, get ue
self.uee = ExtService(model='Exciter',
src='ue',
indexer=self.avr,
tex_name=r'u_{ee}',
info='Effective exciter online status',
)
self.ue = ConstService(v_str='u * uee',
info="effective connection status considering exciter's",
tex_name='u_{e}',
)

self.VCUr = Replace(self.VCU, lambda x: np.equal(x, 0.0), 999)
self.VCLr = Replace(self.VCL, lambda x: np.equal(x, 0.0), -999)

Expand Down Expand Up @@ -83,7 +95,7 @@ def __init__(self, system, config):
# from Exciter
self.vi = ExtAlgeb(model='Exciter', src='vi', indexer=self.avr, tex_name='v_i',
info='Exciter input voltage',
e_str='u * vsout',
e_str='ue * vsout',
ename='Vi',
tex_ename='V_i',
is_input=True,
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6 changes: 3 additions & 3 deletions andes/models/pss/st2cut.py
Original file line number Diff line number Diff line change
Expand Up @@ -160,8 +160,8 @@ def __init__(self, system, config):
)
self.IN = Algeb(tex_name='I_N',
info='Sum of inputs',
v_str='L1_y + L2_y',
e_str='L1_y + L2_y - IN',
v_str='ue * ( L1_y + L2_y )',
e_str='ue * ( L1_y + L2_y )- IN',
)

self.WO = WashoutOrLag(u=self.IN,
Expand Down Expand Up @@ -199,7 +199,7 @@ def __init__(self, system, config):

self.OLIM = Limiter(u=self.v, lower=self.VOL, upper=self.VOU, info='output limiter')

self.vsout.e_str = 'OLIM_zi * VSS_y - vsout'
self.vsout.e_str = 'ue * OLIM_zi * VSS_y - vsout'


class ST2CUT(ST2CUTData, ST2CUTModel):
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