Add bit variable variant

CQCL · Nov 6, 2024 · 6c10d59 · 6c10d59
1 parent dc3539e
commit 6c10d59
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/src/clexpr/operator.rs b/src/clexpr/operator.rs
@@ -51,6 +51,12 @@ pub enum ClVariable {
         /// The register index.
         index: u32,
     },
+    /// A constant bit.
+    #[serde(rename = "bit")]
+    Bit {
+        /// The bit index.
+        index: u32,
+    },
 }
 
 impl Default for ClArgument {