fix mypy

CQCL · Dec 18, 2024 · 54f63a5 · 54f63a5
1 parent d4d3c38
commit 54f63a5
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/pytket/extensions/qiskit/qiskit_convert.py b/pytket/extensions/qiskit/qiskit_convert.py
@@ -663,7 +663,7 @@ def append_tk_command_to_qiskit(
         qb = qregmap[qubit.reg_name][qubit.index[0]]
         b = cregmap[bit.reg_name][bit.index[0]]
         # If the bit is storing a range predicate it should be invalidated:
-        range_preds.pop(bit, None)
+        range_preds.pop(bit, None)  # type: ignore
         return qcirc.measure(qb, b)
 
     if optype == OpType.Reset:

diff --git a/tests/qiskit_convert_test.py b/tests/qiskit_convert_test.py
@@ -1193,7 +1193,7 @@ def test_nonregister_bits() -> None:
         tk_to_qiskit(c)
 
 
-def test_range_preds_with_conditionals():
+def test_range_preds_with_conditionals() -> None:
     # https://github.com/CQCL/pytket-qiskit/issues/375
     c = Circuit(1, 1)
     treg = c.add_c_register(_TEMP_BIT_NAME, 1)