-
Notifications
You must be signed in to change notification settings - Fork 0
TOC Table of Contents
Andy Glew (Dell ) edited this page Jun 17, 2020
·
5 revisions
The github wiki apparently has online macros such as TOC (Table Of Contents) disabled.
That's okay, I've written TOCs for other wikis that operate offline. Not yet using here.
This just a baby first step: links extracted.
- TBD: hand edit to logical structure.
- TBD: delete non-TOC links
- TBD: collect non-linked / non-TOC'ed pages
===
Issues
Dang, no easy crosslinking between Github wiki and issues.
-
https://github.com/AndyGlew/Ri5-stuff/issues/2
- Verify that the recommended partial instruction completion loop constructs for CMOs operate correctly if optional prefetches or hints are treated as NOPs. #2
===
- An-even-quicker-and-dirtier-summary-of-proposed-instruction-encodings-for-RISC-V-CMOs
- Block-memory-operations:-such-as-MEMSET-and-MEMCOPY
- CMO-goals
-
CMOs-(Cache-Management-Operations)
- An even quicker and dirtier summary of proposed instruction encodings for RISC-V CMOs
- CMO-types issue
- Consensus Work in Progress
- Fixed Block Size Prefetches and CMOs
- Instruction Name Choice
- Non-Address Based CMOs for Abstraction and Efficiency
- Overview of CMO operations
- Quick and Dirty Proposal for RISC-V CMOs
- STATUS: almost done? - maybe
- Terminology for instructions that manage microarchitecture state such as caches, prefetchers and predictors
- Variable Address Range CMOs
- CMOs-Not-Based-on-Memory-Address
- CMOs-proportional-to-cache-size-rather-than-address-range
- Extended-CMO-types
- Fixed-Block-Size-Prefetches-and-CMOs
- Home
- ISSUE:-process-migration-argues-for-whole-cache-invalidation-operations-and-against-the-partial-progress-loop-construct
- Instructions-that-Support-Partial-Progress
- Mandatory-versus-Optional-CMOs,-PREFETCHES,-and-CPHs
- Non-Address-Based-CMOs-for-Abstraction-and-Efficiency
- Overview-of-CMO-operations
- Quantization,-dequantization,-and-interpolation-instructions--for-DL,-math,-etc.
-
Quick-and-Dirty-Proposal-for-RISC-V-CMOs
- <cmo_type>
- <virtual/physical>
- CMO goals
- CMO variable address range alternatives
- CMOs Not Based on Memory Address
- CMOs based on cache microarchitecture
- CMOs proportional to cache size rather than address range
- Instantaneous Flushes of Predictor and Cache State
- Transparent Resumeability Prefers SrcDst Register Operands
- full memory addressing mode rs1+imm12 for prefetches and CMOs
- STATUS:-almost-done - maybe
- Sharing-Drawings-and-Diagrams
- Some-Page
-
Terminology-for-instructions-that-manage-microarchitecture-state-such-as-caches,-prefetchers-and-predictors
- At the time of writing pages in this document (wiki)
- BTB
- CMOs (Cache Management Operations)
- CMOs-(Cache-Management-Operations)
- CPH (Cache Performance Hints)
- CPH (Cache Performance Hints) instructions
- HWDS (Hardware Data Structure)
- List of optional versus mandatory CMOs
- Mandatory versus Optional CMOs, PREFETCHES, and CPHs
- PREFETCH instructions
- Performance Related Hardware Data Structure
- Performance Related Hardware Data Structures
- TLB
- at the time of writing
- branch predictor stew
- cache push out or post-store
- clean or flush
- optional prefetches or post-store
- pHWDS
- partial instruction completion loop constructs
- partial instruction completion
- Virtual-or-Physical-CMO-instruction-flavor
- cmo_type-CMO-instruction-flavor
-
hack-relative-URLs-in-github-project-wiki-repo
- ..
- ../../wiki g