Update part name for zcu104.toml, reset port_width (#94)

* Update part name for zcu104.toml * Update solver.py, force port_width = 64
AlexMontgomerie · Jul 17, 2024 · 20d720a · 20d720a
1 parent 6af6879
commit 20d720a
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Showing 2 changed files with 11 additions and 2 deletions.
diff --git a/examples/platforms/zcu104.toml b/examples/platforms/zcu104.toml
@@ -1,7 +1,7 @@
 [device]
 name = "zcu104"
 #family = ""
-part = "xczu7ev-ffvb1156-2-e"
+part = "xczu7ev-ffvc1156-2-e"
 board = "" #TODO: add board file
 
 [resources]

diff --git a/fpgaconvnet/optimiser/solvers/solver.py b/fpgaconvnet/optimiser/solvers/solver.py
@@ -382,7 +382,16 @@ def update_io_port_width(self):
         if not self.constrain_port_width:
             return
 
-        port_width = self.platform.eth_port_width if self.multi_fpga else self.platform.port_width
+        # port_width = self.platform.eth_port_width if self.multi_fpga else self.platform.port_width
+        # force port_width = 64 for now
+        if self.multi_fpga:
+            port_width = self.platform.eth_port_width
+        else: 
+            if (self.net.backend == "hls"):
+                port_width = 64
+            else: port_width = self.platform.port_width 
+
+
         for partition in self.net.partitions:
             ## remove auxiliary layers
             partition.remove_squeeze()