AArch64: Add compensation code to TR_UnloadedClassPicSite

Add compensation code to TR_UnloadedClassPicSite for aarch64. This code uses _size member to check if the site is for address materialization sequence. Unlike arm or ppc, the lsb of the mov instruction of aarch64 is used for encoding the target register number. Thus, we cannot simply set lsb of the patch location to invalidate it. If _size is 4, we patch the pic location to `movz rX, eclipse-openj9#1`. Otherwise, we store -1 to the pic location. Signed-off-by: Akira Saitoh <[email protected]>
Akira1Saitoh · Nov 7, 2019 · 067c52d · 067c52d
1 parent c70ea85
commit 067c52d
Showing 1 changed file with 19 additions and 0 deletions.
diff --git a/runtime/compiler/runtime/ClassUnloadAssumption.cpp b/runtime/compiler/runtime/ClassUnloadAssumption.cpp
@@ -716,6 +716,25 @@ void TR_UnloadedClassPicSite::compensate(TR_FrontEnd *, bool isSMP, void *)
    value |= 0x03a00001;
    *((uint32_t *)_picLocation) = value;
    armCodeSync(_picLocation, 4);
+#elif defined(TR_HOST_ARM64)
+   extern void arm64CodeSync(unsigned char *codeStart, unsigned int codeSize);
+   if (_size == 4)
+      {
+      uint32_t value = *(uint32_t *)_picLocation;
+      // For aarch64, we use _size to check if PICSite is for address materialization sequence.
+      // If _size is 4, we assume the site is the last instruction of address materialization sequence.
+      // We change the instruction to movzx rX, #1
+      // The register number is encoded in bit 0:4.
+      value = 0xd2800020 | (value & 0x1f);
+      *((uint32_t *)_picLocation) = value;
+      arm64CodeSync(_picLocation, 4);
+      }
+   else
+      {
+      // If _size is not 4, the site is a whole pointer.
+      *(int64_t *)_picLocation = -1;
+      arm64CodeSync(_picLocation, 8);
+      }
 #else
    //   TR_ASSERT(0, "unloaded class PIC patching is not implemented on this platform yet");
 #endif