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STM32: check for UART ongoing transfers before entering deepsleep #7717
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When serial is first enabled is the
TC
flag set, or does a transfer actually have to complete for this to be set? If it isn't set then UARTs which are only read from will block deep sleep all the time.There was a problem hiding this comment.
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Hmmm ... Reset value of TC flag is 1. It is set to 0 in case there is a new TX byte or in case it is explicitly cleared by software - which could be the case in serial ASYNCH mode ...
So Maybe I need a specific logic for Asynch ... but for UARTs that are only read, that should be fine.
Extract from spec:
Interrupt and status register (USARTx_ISR)
Address offset: 0x1C
Reset value: 0x0200 00C0
[...]
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USARTx_CR1 register. It is cleared by
software, writing 1 to the TCCF in the USARTx_ICR register or by a write to the
USARTx_TDR register.
An interrupt is generated if TCIE=1 in the USARTx_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note:If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
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Note that in case of asynch I would expect the application or driver using this mode to be in charge of locking deep sleep until Tx is complete - don't you think ?
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I was looking at the datasheet for the
F429
which appears to have different behavior. The transfer complete check may need to be different for each family.Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by
a software sequence (a read from the USART_SR register followed by a write to the
USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing
sequence is recommended only for multibuffer communication.
0: Transmission is not complete
1: Transmission is complete
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I think you've got an old spec. In recent one (rev17), the reset value is 0xC0
https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf
Also I've just done tests (on NUCLEO_F429ZI) using Rx only on 1 UART while printing with another one and this works fine, i.e. Deep sleep is well entered and there is no garbage character at the end of the printed line (deep sleep is actually only entered after the transmission is complete).
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Ah good catch, I had an old version of the datasheet.
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I also had an old one ! ... so it took me some time and tests to figure that out :-)