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[STM32] Rectify IRQ Handling for Serial Devices #4780
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- clear `TxIrq` before calling `irq_handler()` - do not clear `RxIrq` but delegate this to `irq_handler()` (which can do this by simply calling `serial_getc()`) - use correct mask when checking if `TxIrq` is enabled
Unfortunately, both PRs seem not to be with respect to the same base version, so its difficult to compare them. Just to more clear, I am quite sure that PR #4734 does not resolved the TX race condition issue! On the contrary it might introduce an endless busy loop. |
Furthermore, patch in line #450 seems not to be catched! |
In your place I would stop the merge of PR #4734 and review it! |
Then could you please help and make your comments in #4734 ? |
Typically your PR address
|
No, I think you need to clear it before calling the irq handler (i.e.
Ok.
Or inserted in yours. |
I also think that you should not leave it up to the higher level irq handler (or application) to clear it, because most likely there is no API for doing so and further there is mbed code which does rely on the lower level device driver to clear it (e.g. |
@betzw - ok clear now, thanks. |
@betzw - I'm curious about you singling out ATParser. The original patch was tested with UARTSerial, whose interrupt handlers were derived from the BufferedSerial in ATParser. Those interrupt handlers take care to ensure the interrupt condition is cleared in the UART by reading all data or making sure they write until full, and disabling the TX interrupt if nothing left to send. The interrupt must be unlatched manually in the HAL if accessing the UART is not sufficient to unlatch a pending condition, but in this case I believe there is no need for it - data register accesses are sufficient. However, it sounds plausible that a manual clear before calling the handler would cover cases where the handler failed to clear the condition. (At a slight performance cost). |
So, if I understand correctly you agree upon clearing the IRQ before calling the higher lever handler, correct? |
@betzw Some update after I looked into required updates to #4734 as discussed in this post yesterday There are 2 aspects in #4734, 1) do not clear RXNE flag or that would cause possible data loss, and 2) move TxIrq to TXE interrupt (Tx Data register empty) instead of TC (transmission complete) because this is the way it is defined in MBED API and also this improves overall perf. Because of 2) above I think that your comments on #4734 cannot be applied. => use correct mask USART_CR1_TCIE when checking if TxIrq is enabled Let me know your thoughts - also maybe could you actually run your tests using the version from #4734 and check if working ok ? |
@LMESTM OK for me! |
@betzw It looks like you have a conflict. Could you rebase to resolve this conflict? |
I would prefer to wait for @LMESTM comments on this! |
@betzw Hi. I don't know about Wifi driver so it's hard to tell. So when using TXE as recommended in MBED, you may need to check:
Is is possible that any of the 2 above points could happen in your case ? |
@LMESTM not sure if I understood everything ...
Could you pls. elaborate on this.
Do you mean that using |
@betzw Concerning TXE usage, TxIrq in SerialBase Class is defined as "TxIrq for transmit buffer empty" One year back (when raising the shared issues) I suggested to use TC instead for reliability but the proposals were rejected because of performance degradation, typically with classes like BufferedSerial which indeed assume that TxIrq means "Tx buffer empty". Maybe the list of interrupts may be updated to also add TxCompleteIrq which would allow application to select the one it needs. Could you try to check if the data loss still happens in case you disable sleep modes ? |
Well, following what an renowned HW engineer said to me when I was discussing with him about this issue, there is no significant difference between using
This is true also when
The executable is already compiled with |
And no, no GPIO signaling is used after that the WiFi module is reset at startup. |
@LMESTM, I have just taken a look on one of the MCU reference manual and have found the following: After writing the last data into the USART_DR register, it is mandatory to wait for TC=1 |
And also before entering sleep mode or trying to change baudrate or switch clock off or also before releasing or re-using the buffer that is being transmitted ... Does the wifi driver do anything close to this ? Can you point to the code that is making use of Serial API and which hits the issue ? My only guess is that there is a need to "wait" after sending the data until we have a API to be informed that Tx is complete (and then you'll have to use this API) To cope with every requirements, the Serial API should be extended to offer the API to clearly distinguish between "Room in Tx buffer" and "Tx complete". There have been similar discussions in other systems https://lists.zephyrproject.org/pipermail/zephyr-devel/2017-May/007642.html |
With respect to the serial/usart the WiFi driver itself doesn't do much with it directly. All is delegated to mbed class |
Description
STM32's serial device drivers currently feature some race conditions which might lead to loose interrupts coming from the serial device.
Status
READY
Fixes
TxIrq
before callingirq_handler()
RxIrq
but delegate this toirq_handler()
(which is usually done by the higher level interrupt handler
irq_handler()
by simply callingserial_getc()
)USART_CR1_TCIE
when checking ifTxIrq
is enabledNote
This PR just fixes the issue for STM32F4 but is likely to be needed to be applied for all STM32 platfroms.
CCs
@bcostm, @adustm, @LMESTM, @nikapov-ST, @screamerbg