Merge pull request #1848 from TomoYamanaka/master

Implement SystemcoreClock
ARMmbed · Jun 13, 2016 · e9b5601 · e9b5601
2 parents ab5bd79 + 8f3e72f
commit e9b5601
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diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
@@ -49,8 +49,15 @@ void FPUEnable(void);
 
 #endif
 
+#define FRQCR_IFC_MSK          (0x0030)
+#define FRQCR_IFC_SHFT         (8)
+#define FRQCR_IFC_1P1          (0) /* x1/1 */
+#define FRQCR_IFC_2P3          (1) /* x2/3 */
+#define FRQCR_IFC_1P3          (3) /* x1/3 */
+
 uint32_t IRQNestLevel;
 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
 
 
 /**
@@ -198,6 +205,35 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq)
     }
 }
 
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+    switch (frqcr_ifc) {
+        case FRQCR_IFC_1P1:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+            break;
+        case FRQCR_IFC_2P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+            break;
+        case FRQCR_IFC_1P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
+            break;
+        default:
+            /* do nothing */
+            break;
+    }
+}
+
+
 /**
  * Initialize the system
  *

diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h
@@ -43,6 +43,8 @@
 extern "C" {
 #endif
 
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
 typedef void(*IRQHandler)();
 uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
 uint32_t InterruptHandlerUnregister(IRQn_Type);

diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c
@@ -49,8 +49,15 @@ void FPUEnable(void);
 
 #endif
 
+#define FRQCR_IFC_MSK          (0x0030)
+#define FRQCR_IFC_SHFT         (8)
+#define FRQCR_IFC_1P1          (0) /* x1/1 */
+#define FRQCR_IFC_2P3          (1) /* x2/3 */
+#define FRQCR_IFC_1P3          (3) /* x1/3 */
+
 uint32_t IRQNestLevel;
 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
 
 
 /**
@@ -198,6 +205,35 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq)
     }
 }
 
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+    switch (frqcr_ifc) {
+        case FRQCR_IFC_1P1:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+            break;
+        case FRQCR_IFC_2P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+            break;
+        case FRQCR_IFC_1P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
+            break;
+        default:
+            /* do nothing */
+            break;
+    }
+}
+
+
 /**
  * Initialize the system
  *

diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h
@@ -43,6 +43,8 @@
 extern "C" {
 #endif
 
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
 typedef void(*IRQHandler)();
 uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
 uint32_t InterruptHandlerUnregister(IRQn_Type);